參數(shù)資料
型號: MB90F372PMT-G
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數(shù): 80/153頁
文件大?。?/td> 1573K
代理商: MB90F372PMT-G
MB90370 Series
80
16. LPC interface
The LPC (Low Pin Count) interface consists of an LPC bus interface, universal parallel interface (UPI x 4
channels), gate address A20 function and LPC data buffer array. By using the LPC bus interface and UPI, data
can be exchanged with an external host CPU synchronously via an external LPC bus.
LPC bus interface
The LPC bus interface provides direct access of host CPU to UPI.
It supports I/O read and I/O write cycle only. Other cycle types will be ignored.
It supports LPC clock running at 33 MHz.
Universal parallel interface, UPI x 4 channels
The UPI is used to exchange parallel data to serial data in LPC bus with host CPU.
An 8-bit data will be transmitted or received.
A buffer function is available for independent input and output.
The I/O buffer status can be output externally through LPC bus interface.
Gate address A20 function for UPI channel 0
The GA20 (Gate Address A20) is intended to implement the memory management in a PC architecture.
This allows the access to the extended memory needed by the operating system. On-chip logic is provided
to speed up the generation of GA20.
Data buffer array
The data buffer array is consisted of 32 bytes UP data register and 16 bytes DOWN data register to speed
up the data transfer between MCU and external host through LPC bus.
(1) Register configuration of LPC bus interface register
7
6
5
4
3
2
1
0
Bit number
LPC Control Register
Address:
00006E
H
R/W
0
Initial value
Read/write
LCR
LPE
LRIE
LRF
R/W
0
R/W
0
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