參數資料
型號： MB90F372
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數： 88/140頁
文件大?。?/td> 650K
代理商： MB90F372
MB90370/375 Series
88
17. Serial IRQ controller
The serial IRQ controller consists of a 6-channel serial IRQ control circuit and an LPC clock monitor
/
control
circuit. By using this serial IRQ controller, host interrupt requests can be transferred serially through a single
signal wire (SERIRQ) , synchronized with the LPC clock.
6-channel serial IRQ control circuit
The 6-channel serial IRQ control circuit consists of a serial interrupt control register (SICR) , 4 serial interrupt
frame number registers (SIFR1 to SIFR4) , a protocol state machine and a serial interrupt data latch and output
control.
For channel 0A, 0B and 1 to 3, if SICR : OBE bit (OBF controlled enable bit)
=
0, then serial IRQ can be
controlled by software setting of SICR : IRR bit. If SICR : OBE bit
=
1, then software control is disabled and
serial IRQ is controlled by OBF flag (Output buffer full flag) from LPC UPI0 to UPI3.
For channel 4, serial IRQ can be controlled by software setting of SICR : IRR bit.
For channel 0A and 0B, additional enable bit (SICR : EN0A/0B bit) can be used to latch and keep the OBF0
or IRR0A/0B bit status.
The serial interrupt data latch transfers serial IRQs serially according to their frame number. The frame number
for channel 0A is fixed to “IRQ1”, for channel 0B is fixed to “IRQ12”, and the frame number for channel 1 to
channel 4 are software programmable (IRQ1 to IRQ15, and IRQ21 to IRQ31) by setting the SIFR1 to SIFR4.
By monitoring the SERIRQ and the LPC clock pin, the protocol state machine can detect the START frame
condition. Then it starts counting the DATA frame and transfers its serial IRQs through SERIRQ. Finally it can
switch to continuous/quiet mode operation by determine the STOP frame condition.
The serial interrupt output control support both continuous and quiet mode operation. In continuous mode
operation, only the host can initiate the serial IRQs transfer; In quiet mode operation, both the host and slave
(e.g. the serial IRQ controller) can initiate the serial IRQs transfer.
LPC clock monitor
/
control circuit
The LPC clock monitor
/
control circuit consists of a clock-run monitor
/
control circuit. By monitoring the clock-
run pin (CLKRUN) , the clock monitor
/
control circuit can determine whether the host has stopped LPC clock
in quiet mode operation or not. If LPC clock is stopped and the controller wants to initiate the serial IRQs
transfer, then it can request the host to restart the LPC clock by controlling the CLKRUN pin.
相關PDF資料
PDF描述
MB90F372PFF-G 16-bit Proprietary Microcontroller
MB90F377 16-bit Proprietary Microcontroller
MB90F377PFF-G 16-bit Proprietary Microcontroller
MB90F378 16-bit Proprietary Microcontroller
MB90F378PFF-GE1 16-bit Proprietary Microcontroller
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