參數(shù)資料
型號(hào): MB90F372
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數(shù): 101/140頁
文件大小: 650K
代理商: MB90F372
MB90370/375 Series
101
22. DTP/External interrupts
The DTP (Data Transfer Peripheral) /external interrupt circuit is activated by the signal supplied to a DTP/external
interrupt pin. The CPU accepts the signal using the same as procedure used for normal hardware interrupts
and generates external interrupts or activates the extended intelligent I/O service (EI
2
OS) .
Features of DTP/External interrupt :
Total 6 external interrupt channels
Two request levels (“H” and “L”) are provided for the intelligent I/O service.
Four request levels (rise/fall edge, fall edge, “H” level and “L” level) are provided for external interrupt requests .
(1) Register configuration
DTP/Interrupt Source Register
DTP/Interrupt Enable Register
Request Level Setting Register (Upper)
Request Level Setting Register (Lower)
Bit number
EIRR
Address : 000027
H
Read/write
Initial value
Bit number
ENIR
Address : 000026
H
Read/write
Initial value
Bit number
ELVRH
Address : 000029
H
Read/write
Initial value
Bit number
ELVRL
Address : 000028
H
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
ER5
ER4
ER3
ER2
ER1
ER0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
EN5
EN4
EN3
EN2
EN1
EN0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
LB5
LA5
LB4
LA4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
LA3
R/W
0
LB3
LB2
LA2
LB1
LA1
LB0
LA0
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