參數(shù)資料
型號(hào)： MB90F244PFT-G
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： Octal Edge-Triggered D-type Flip-Flops With Clock Enable 20-LCCC -55 to 125
中文描述： 16-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 61/67頁
文件大小： 1403K
代理商： MB90F244PFT-G
61
MB90F244
Table 22 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle
DTB: 2 cycles
DPR: 3 cycles
*2: 3 + 4
×
(pop count)
*3: 3 + 4
×
(push count)
*4: Pop count
×
(c), or push count
×
(c)
*5: 3 when AL is 0, 5 when AL is not 0.
*6: 4 when AL is 0, 6 when AL is not 0.
*7: 5 when AL is 0, 7 when AL is not 0.
Mnemonic
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
POPW A
POPW AH
POPW PS
POPW rlst
JCTX
@A
AND
OR
CCR, #imm8
CCR, #imm8
MOV RP #imm8
MOV ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
ADDSP #imm8
ADDSP #imm16
MOV
MOV
MOV
A, brgl
brg2, A
brg2, #imm8
NOP
ADB
DTB
PCB
SPB
NCC
CMR
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
CLRSPC
BTSCN A
BTSCNSA
BTSCNDA
1
1
1
2
1
1
1
2
1
2
2
2
2
2
2+
2
2+
2
3
2
2
3
1
1
1
1
1
1
1
4
4
2
2
2
2
2
3
3
3
*
3
3
3
3
*
2
9
3
3
2
2
3
2+ (a)
2
1+ (a)
3
3
*
1
1
2
1
1
1
1
1
1
1
2
2
2
2
*
5
*
6
*
7
(c)
(c)
(c)
*
4
(c)
(c)
(c)
*
4
6
×
(c)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
word (SP)
←
(SP) –2, ((SP))
←
(A)
word (SP)
←
(SP) –2, ((SP))
←
(AH)
word (SP)
←
(SP) –2, ((SP))
←
(PS)
(SP)
←
(SP) –2n, ((SP))
←
(rlst)
word (A)
←
((SP)), (SP)
←
(SP) +2
word (AH)
←
((SP)), (SP)
←
(SP) +2
word (PS)
←
((SP)), (SP)
←
(SP) +2
(rlst)
←
((SP)) , (SP)
←
(SP)
Context switch instruction
byte (CCR)
←
(CCR) and imm8
byte (CCR)
←
(CCR) or imm8
byte (RP)
←
imm8
byte (ILM)
←
imm8
word (RWi)
←
ear
word (RWi)
←
eam
word(A)
←
ear
word (A)
←
eam
word (SP)
←
ext (imm8)
word (SP)
←
imm16
byte (A)
←
(brgl)
byte (brg2)
←
(A)
byte (brg2)
←
imm8
No operation
Prefix code for AD space access
Prefix code for DT space access
Prefix code for PC space access
Prefix code for SP space access
Prefix code for no flag change
Prefix code for the common register bank
word (SPCU)
←
(imm16)
word (SPCL)
←
(imm16)
Stack check operation enable
Stack check operation disable
byte (A)
←
position of “1” bit in word (A)
byte (A)
←
position of “1” bit in word (A)
×
2
byte (A)
←
position of “1” bit in word (A)
×
4
–
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Z
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Z
Z
Z
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*
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