參數(shù)資料
型號(hào): MB90947APF
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 51/72頁(yè)
文件大?。?/td> 1586K
代理商: MB90947APF
MB90945 Series
DS07-13741-3E
55
(8) I2C Timing
(TA
= 40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the devie does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
Parameter
Symbol Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.3 k,
C
= 50 pF*1
01000400
kHz
Hold time (repeated) START condition
SDA
↓ → SCL ↓
tHDSTA
4.0
0.6
s
“L” width of SCL clock
tLOW
4.7
1.3
s
“H” width of SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑ → SDA ↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↑ → SDA ↓↑
tHDDAT
03.45*2
00.9*3
s
Data set-up time
SDA
↓↑ → SCL ↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑ → SDA ↑
tSUSTO
4.0
0.6
s
Bus free time between STOP and START
condition
tBUS
4.7
1.3
s
SDA
SCL
tLOW
tHIGH
tHDDAT
tHDSTA
tSUDAT
tSUSTA
tHDSTA
tSUSTO
tBUS
I2C Timing
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