參數(shù)資料
型號: MB90947APF
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 46/72頁
文件大小: 1586K
代理商: MB90947APF
MB90945 Series
50
DS07-13741-3E
Bit setting : ESCR : SCES
= 1, ECCR : SCDE = 0
(TA
= 40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP.
Parameter
Sym-
bol
Pin
Condition
Value
Unit Remarks
Min
Max
Serial clock cycle time
tSCYC
SCK2,SCK3
Internal clock
operation output
pins are
CL
= 80 pF + 1 TTL.
5 tCP
ns
SCK
↑ → SOT delay time
tSHOVI
SCK2,SCK3
SOT2,SOT3
50
+50
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK2,SCK3
SIN2,SIN3
tCP
+ 80
ns
SCK
↓ → Valid SIN hold time
tSLIXI
SCK2,SCK3
SIN2,SIN3
0
ns
Serial clock “H” pulse width
tSHSL
SCK2,SCK3
External clock
operation output
pins are
CL
= 80 pF + 1 TTL.
3 tCP
tR
ns
Serial clock “L” pulse width
tSLSH
SCK2,SCK3
tCP
+ 10
ns
SCK
↑ → SOT delay time
tSHOVE
SCK2,SCK3
SOT2,SOT3
2 tCP
+ 60 ns
Valid SIN
→ SCK ↓
tIVSLE
SCK2,SCK3
SIN2,SIN3
30
ns
SCK
↓ → Valid SIN hold time tSLIXE
SCK2,SCK3
SIN2,SIN3
tCP
+ 30
ns
SCK fall time
tF
SCK2,SCK3
10
ns
SCK rise time
tR
SCK2,SCK3
10
ns
SCK
VIH
VIL
SOT
0.8 V
2.4 V
tSLOVE
SIN
VIL
VIH
VIL
VIH
VIL
tR
tF
tSHSL
tSLSH
tIVSHE
tSHIXE
External Shift Clock Mode
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