參數(shù)資料
型號(hào)： MB90670
廠商： Fujitsu Limited
英文描述： Scan Test Devices With Octal Bus Transceivers And Registers 28-CDIP -55 to 125
中文描述： 16位微控制器專(zhuān)有
文件頁(yè)數(shù)： 72/106頁(yè)
文件大?。?/td> 1648K
代理商： MB90670
MB90670/675 Series
72
16. Low-power Consumption (Standby) Mode
The F
2
MC-16L has the following CPU operating mode configured by selection of an operating clock and clock
operation control.
Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock (HCLK).
Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the
oscillation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
Hardware stand-by mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply (sleep mode)
to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode).
Of these modes, modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
Clock select register (CKSCR)
Address
0000A1
H
bit 7 . . . . . . . . . . . .
RESV
MCM
WS1
WS0
RESV
MCS
CS1
CS0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
(LPMCR)
R/W
R
R/W
R/W
R/W
R/W
W
R/W
Address
0000A0
H
bit 15 . . . . . . . . . . . .
STP
SLP
SPL
RST
RESV
CG1
CG0
RESV
(CKSCR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
W
R/W
W
R/W
R/W
R/W
R/W
R/W : Readable and writable
R : Read only
W : Write only
Low-power consumption mode control register (LPMCR)
Initial value
00011000
B
Initial value
11111100
B
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