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參數(shù)資料
| 型號(hào)： | MB90662APFM |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 0.65 MM PITCH, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 148/284頁(yè) |
| 文件大?。?/td> | 2703K |
| 代理商： | MB90662APFM |
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3.5 Low Power Consumption Modes
226
Chapter 3:Operation
In stop mode, the contents of dedicated registers (such as accumulators) and internal RAM are retained.
q Wake-up from Stop Mode
The standby control circuit performs wake-up from stop mode at input of a reset signal or occurrence of
an interrupt. If stop mode is exited by a reset source, the MB90660A will be in reset state when it wakes
up from stop mode.
For wake-up from stop mode, the standby control circuit will move first to oscillation stabilization wait
mode prior to wake-up from stop mode. Also, if a reset source is the cause for wake-up from stop mode,
the reset sequence is initiated after an oscillation stabilization wait interval before the reset is applied.
During stop mode, any interrupt request stronger (higher) than level 7 generated from a peripheral
circuit or any other source can wake up the MB90660A from stop mode. The wake-up sequence first
passes into an oscillation stabilization interval defined by the WS1, WS0 bits in the CKSCR register,
then follows the normal interrupt processing sequence. If the interrupt request is accepted according to
the values of the I flag, ILM bit and interrupt control register (ICR), the CPU will branch to interrupt
processing. If the interrupt is not accepted, execution will continue with the next instruction following
the instruction that caused the transition to stop mode.
[CAUTION]
When interrupt processing is executed, the normal procedure is to first execute the
instruction following the instruction that caused the transition to stop mode before
branching to interrupt processing.
(4) CPU Intermittent Operation Function
The CPU intermittent operation function allows the clock signal feed to the CPU to operate
intermittently for registers, internal memory (ROM, RAM, I/O, or resource memory) or external bus
access. This function delays the start of the internal bus cycle by introducing a fixed pause in the clock
signal feed, thus reducing power consumption by lowering the CPU execution speed while maintaining
the high speed clock feed to the internal resources. The CG1, CG0 bits select the number of fixed pause
cycles in the clock feed to the CPU.
Note that external bus operations continue to use the same clock signal as the peripheral resources.
Instruction execution time using the CPU intermittent operation function can be calculated by adding
the number of access cycles to register, internal memory and internal resources to the normal execution
time increased by a fixed number of cycles in each pause.
Peripheral clock
CPU clock
Intermittent operation temporary
Internal bus startup cycle
pause cycle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90662AP-SH | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP64 |
| MB90P663AP-SH | 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP64 |
| MB90673PF | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| MB90T673PF | 16-BIT, 16 MHz, MICROCONTROLLER, PQFP80 |
| MB90671PFV | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90662AP-SH | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90663A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90663APFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller CMOS |
| MB90663AP-SH | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller CMOS |
| MB90670 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-Bit Proprietary Microcontroller |
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