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參數(shù)資料
| 型號(hào)： | MB90660A |
| 廠商： | Fujitsu Limited |
| 英文描述： | UL/CSA, T-BEAM, D-ON |
| 中文描述： | 16位微控制器專有的CMOS |
| 文件頁數(shù)： | 26/83頁 |
| 文件大?。?/td> | 820K |
| 代理商： | MB90660A |
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26
MB90660A Series
I
PERIPHERAL RESOURCES
1. Parallel Port
The MB90660A includes 39 I/O pins, 4 input pins, and 8 open-drain output pins.
Port 0, 1, 2, 3 and 6 are I/O ports. They are used for input when the corresponding direction register value is
“0”, and for output when the value is “1”.
Port 5 is an open-drain port. It is used as a port when the analog input enable register is “0”.
Ports 40 to 43 are I/O ports. They are used for input when the corresponding direction register value is “0”, and
for output when the value is “1”. Ports 44 to 47 are input ports which can only be used for reading data.
(1) Register Configuration
Notes: There are no register bits for bits 15 to 12 of Port 3.
There is no register bit for bit 7 of Port 6.
Bits 7 to 4 of Port 4 can only be used to read data.
bit
Read/Write
Initial value
bit
PD
×
7 PD
×
6 PD
×
5 PD
×
4 PD
×
3 PD
×
2 PD
×
1 PD
×
0
PDR1, 3
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
PD
×
7 PD
×
6 PD
×
5 PD
×
4 PD
×
3 PD
×
2 PD
×
1 PD
×
0
PDR0, 2, 6
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
Read/Write
Initial value
bit
Read/Write
Initial value
bit
Read/Write
Initial value
PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50
PDR5
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
15
14
13
12
11
10
9
8
PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40
PDR4
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
Port Data Register
Address: PDR1 000001
H
: PDR3 000003
H
Port Data Register
Address: PDR0 000000
H
: PDR2 000002
H
: PDR6 000006
H
(PDBR)
Port Data Register
Address: 000005
H
Port Data Register
Address: 000004
H
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