參數(shù)資料
型號: MB90653APFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: Scan Test Devices With Octal Bus Transceivers And Registers 28-CDIP -55 to 125
中文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 69/120頁
文件大?。?/td> 1690K
代理商: MB90653APFV
69
MB90650A Series
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F
2
MC-16L CPU can be generated and cleared by software using this module.
(1) Register Details
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(2) Block Diagram
Address : 00009F
H
R0
R/W
Initial value
-------0
B
Delayed interrupt generation /release register (DIRR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
: Readable and writable
: Unused
Delayed interrupt generation/release decoder
Interrupt latch
I
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