參數(shù)資料
型號: MB90653APFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: Scan Test Devices With Octal Bus Transceivers And Registers 28-CDIP -55 to 125
中文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 36/120頁
文件大?。?/td> 1690K
代理商: MB90653APFV
36
MB90650A Series
(5) Port Pin Register
Register configuration
Block diagram
(6) Analog Input Enable Register
Register configuration
Controls each port 5 pin as follows.
0: Port input mode
1: Analog input mode
Set to “1” by a reset.
: Readable and writable
: Unused
OD46
OD45
OD44
OD43
OD42
OD41
OD40
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 00001B
H
Port 4 pin register (ODR4)
Initial value Access
-0000000
B
R/W
R/W
Data register
Direction register
Port I/O
Pin register
I
Notes:
Pin register R/W
Performs open-drain control in output mode.
0: Operate as a standard output port in output mode.
1: Operate as an open-drain output port in output mode.
The setting has no meaning in input mode (output Hi-z).
The direction register (DDR) sets input or output mode.
This function is disabled when using an external bus mode. In this case, do not write to this register.
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W : Readable and writable
Address : 00001F
H
Analog input enable register (ADER)
Initial value
11111111
B
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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