參數(shù)資料
型號(hào): MB90653APFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: Scan Test Devices With Octal Bus Transceivers And Registers 28-CDIP -55 to 125
中文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁(yè)數(shù): 27/120頁(yè)
文件大?。?/td> 1690K
代理商: MB90653APFV
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27
MB90650A Series
(Continued)
Address
Register
Register
name
Read/
write
Resource name
Initial value
51
H
Upper compare register channel 0
OCCP0
R/W
16-bit I/O timer
Output compare
(channel 0 to channel 3)
XXXXXXXX
B
52
H
Lower compare register channel 1
OCCP1
R/W
XXXXXXXX
B
53
H
Upper compare register channel 1
XXXXXXXX
B
54
H
Lower compare register channel 2
OCCP2
R/W
XXXXXXXX
B
55
H
Upper compare register channel 2
XXXXXXXX
B
56
H
Lower compare register channel 3
OCCP3
R/W
XXXXXXXX
B
57
H
Upper compare register channel 3
XXXXXXXX
B
58
H
Compare control status register channel 0
OCS0
R/W
0000––00
B
59
H
Compare control status register channel 1
OCS1
R/W
–––00000
B
5A
H
Compare control status register channel 2
OCS2
R/W
0000––00
B
5B
H
Compare control status register channel 3
OCS3
R/W
–––00000
B
5C
H
to 5F
H
(Reserved area)
60
H
Lower input capture register channel 0
IPCP0
R
16-bit I/O timer
Input capture
(channel 0, channel 1)
XXXXXXXX
B
61
H
Upper input capture register channel 0
R
XXXXXXXX
B
62
H
Lower input capture register channel 1
IPCP1
R
XXXXXXXX
B
63
H
Upper input capture register channel 1
R
XXXXXXXX
B
64
H
Input capture control status register
ICS0, 1
R/W
00000000
B
65
H
(Reserved area)
66
H
Lower timer data register
TCDTL
R/W
16-bit I/O timer
Free-run timer
00000000
B
67
H
Upper timer data register
TCDTH
R/W
00000000
B
68
H
Timer control status register
TCCS
R/W
00000000
B
69
H
to 6F
H
(Reserved area)
70
H
Up/down count register channel 0
UDCR0
R
8/16-bit up/down
counter/timer
00000000
B
71
H
Up/down count register channel 1
UDCR1
00000000
B
72
H
Reload compare register channel 0
RCR0
W
00000000
B
73
H
Reload compare register channel 1
RCR1
00000000
B
74
H
Counter status register channel 0
CSR0
R/W
00000000
B
75
H
(Reserved area)
76
H
Counter control register channel 0
CCRL0
R/W
8/16-bit up/down
counter/timer
00001000
B
77
H
CCRH0
00000000
B
78
H
Counter status register channel 1
CSR1
R/W
00000000
B
79
H
(Reserved area)
7A
H
Counter control register channel 1
CCRL1
R/W
8/16-bit up/down
counter/timer
00000000
B
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