參數(shù)資料
型號(hào)： MB90634APF
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 99/107頁(yè)
文件大?。?/td> 1599K
代理商： MB90634APF
MB90630A Series
91
Table 4
Number of Execution Cycles for Each Type of Addressing
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
Notes:
“(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Notes:
When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
Code
Operand
(a)
Number of register
accesses for each type of
addressing
Number of execution cycles
for each type of addressing
00 to 07
Ri
RWi
RLi
Listed in tables of instructions
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
2
1
2
0
Operand
(b) byte
(c) word
(d) long
Number
of cycles
Number
of
access
Number
of cycles
Number
of
access
Number
of cycles
Number
of
access
Internal register
+01+01+02
Internal memory even address
Internal memory odd address
+0
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+11+42+84
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
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相關(guān)代理商/技術(shù)參數(shù)
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