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參數(shù)資料
| 型號(hào)： | MB90634APF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 63/107頁 |
| 文件大?。?/td> | 1599K |
| 代理商： | MB90634APF |
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59
MB90630A Series
12. Timebase Timer
The timebase timer consists of an 18-bit timebase counter (which divides the system clock) and a control register.
The carry signal of the timebase counter can generate a fixed period interrupt.
All bits of the timebase counter are cleared to zero at power-on, when stop mode is set, or by software (by writing
“0” to the TBR bit). The timebase counter continuously increments while an oscillation is input.
The timebase counter is also used as the clock source for the watchdog timer and as a timer for the oscillation
stabilization delay time.
(1) Block Diagram
See “(1) Block diagram” in “11. Watchdog Timer” for the block diagram of the timebase timer.
(2) Register Configuration
(3) Register Details
TBTC (Timebase timer control register)
(a) [bit 15] Reserved
A reserved bit. Always set to “1” when writing data to the register.
(b) [bit 12] TBIE
Interval interrupt enable bit for the timebase timer. The interrupt is enabled when TBIE is “1” and disabled
when TBIE is “0”. Initialized to “0” by a reset. The bit is readable and writable.
(c) [bit 11] TBOF
Interrupt request flag for the timebase timer. An interrupt request is generated if TBCF goes to “1” when
TBIE is “1”. The bit is set to “1” at fixed intervals set by the TBC1 and 0 bits. Clear by writing “0”, transition
to stop or hardware standby mode, or a reset. Writing “1” has no meaning.
Read as “1” by read-modify-write instructions.
(d) [bit 10] TBR
Clears all bits of the timebase counter to “0”. Writing “0” to the TBR bit clears the timebase counter. Writing
“1” to the TBR bit is meaningless. Reading from the TBR bit results in “1”.
(e) [bit 9, 8] TBC1, 0
Set a timebase timer interval. The bits are initialized to “00” by resetting. These bits are readable and writable.
Setting of timebase timer interval
TBC1
TBC0
Interval time when base
frequency is 4 MHz
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
131.072 ms
15
14
13
12
11
10
9
8
0000A9H
bit
Reserved
—
TBIE
TBCF
TBR
TBC1
TBC0
Address:
Timebase timer control register
(TBTC)
15
14
13
12
11
10
9
8
0000A9H
bit
Reserved
——
TBIE
TBCF
TBR
TBC1
TBC0
Address:
Initial value
X--00000B
(W)
(R/W)
(W)
(R/W)
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PDF描述 |
|---|---|
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| MB90P641APF | 16-BIT, OTPROM, 17 MHz, MICROCONTROLLER, PQFP100 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90634APFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90641A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90641APF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90641APFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90652A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
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