參數(shù)資料
型號: MB90634APF
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 66/107頁
文件大?。?/td> 1599K
代理商: MB90634APF
61
MB90630A Series
14. Low-Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization
Delay Time, and Clock Multiplier Function)
The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode,
main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are
classified as low power consumption modes.
In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock).
The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the
operating clock.
In PLL sleep mode and main sleep mode, the CPU’s operating clock only is stopped and other elements continue
to operate.
In timer mode, only the timebase timer operates.
Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum
power consumption.
The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal memory,
internal resource, or external bus access is performed. This function reduces power consumption by lowering
the CPU execution speed while still providing a high-speed clock to internal resources.
The PLL clock multiplier ratio can be set to 1, 2, 3, or 4 by the CS1, 0 bits.
The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop
mode or hardware standby mode.
(1) Register Configuration
0000A0H
7654321
STP
SLP
SPL
RST
Reserved
CG1
CG0
Reserved
0
(R/W)
(W)
(R/W)
(W)
(R/W)
(W)
(—)
(0)
(1)
(0)
Address:
LPMCR
Low-power consumption mode register
Read/write
Initial value
0000A1H
15
14
13
12
11
10
9
Reserved
MCM
WS1
WS0
Reserved
MCS
CS1
CS0
8
(R/W)
(—)
(R/W)
(R)
(R/W)
(—)
(R/W)
(1)
(0)
(1)
(0)
(1)
Address:
CKSCR
Clock select register
Read/write
Initial value
bit
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