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參數(shù)資料
| 型號(hào)： | MB90548PFF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 59/73頁(yè) |
| 文件大?。?/td> | 1663K |
| 代理商： | MB90548PFF |
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MB90540/545 Series
62
Table 15
Logical 2 Instructions (Long Word) [6 Instructions]
Table 16
Sign Inversion Instructions (Byte/Word) [6 Instructions]
Table 17
Normalize Instruction (Long Word) [1 Instruction]
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic
#
~
RG
BOperation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A, ear
ANDL
A, eam
ORL
A, ear
ORL
A, eam
XORL A, ea
XORL A, eam
2
2+
2
2+
2
2+
6
7+ (a)
6
7+ (a)
6
7+ (a)
2
0
2
0
2
0
(d)
0
(d)
0
(d)
long (A)
← (A) and (ear)
long (A)
← (A) and (eam)
long (A)
← (A) or (ear)
long (A)
← (A) or (eam)
long (A)
← (A) xor (ear)
long (A)
← (A) xor (eam)
–
*
R
–
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
NEG
A
NEG
ear
NEG
eam
1
2
2+
2
3
5+ (a)
0
2
0
2
× (b)
byte (A)
← 0 – (A)
byte (ear)
← 0 – (ear)
byte (eam)
← 0 – (eam)
X
–
*
–
*
NEGW A
NEGW ear
NEGW eam
1
2
2+
2
3
5+ (a)
0
2
0
2
× (c)
word (A)
← 0 – (A)
word (ear)
← 0 – (ear)
word (eam)
← 0 – (eam)
–
*
–
*
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
NRML A, R0
2
*1
1
0
long (A)
← Shift until first digit is “1”
byte (R0)
← Current shift count
––––––
*
–
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