參數(shù)資料
型號(hào)： MB90548PFF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁(yè)數(shù)： 39/73頁(yè)
文件大?。?/td> 1663K
代理商： MB90548PFF
MB90540/545 Series
44
(8) Hold Timing
(VCC
= 4.5 V to 5.5 V, VSS = 0 V, TA = 40 °C to +85 °C)
Note: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
(9) UART0/1, Serial I/O Timing
(VCC
= 4.5 V to 5.5 V, VSS = 0 V, TA = –40 °C to +85 °C)
Note:
1. AC characteristic in CLK synchronized mode.
2. CL is load capacity value of pins when testing.
3. tCP is the machine cycle (Unit: ns).
Parameter
Symbol
Pin
Condition
Value
Units
Remarks
Min.
Max.
Pin floating
HAK ↓ time
tXHAL
HAK
—
30
tCP
ns
HAK
↑ time Pin valid time
tHAHV
HAK
tCP
2 tCP
ns
Parameter
Symbol
Pin Symbol
Condition
Value
Units Remarks
Min.
Max.
Serial clock cycle time
tSCYC
SCK0 to SCK2
Internal clock opera-
tion output pins are
CL = 80 pF + 1 TTL.
8 tCP
—ns
SCK
↓ SOT delay time
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
–80
80
ns
Valid SIN
SCK ↑
tIVSH
SCK0 to SCK2,
SIN0 to SIN2
100
—
ns
SCK
↑ Valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
Serial clock "H" pulse width
tSHSL
SCK0 to SCK2
External clock oper-
ation output pins are
CL = 80 pF + 1 TTL.
4 tCP
—ns
Serial clock "L" pulse width
tSLSH
SCK0 to SCK2
4 tCP
—ns
SCK
↓ SOT delay time
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
—
150
ns
Valid SIN
SCK ↑
tIVSH
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
SCK
↑ Valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
HAK
Each pin
High impedance
tHAHV
tXHAL
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
Hold Timing
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