
MB90540/545 Series
3
s PRODUCT LINEUP
The following table provides a quick outlook of the MB90540/545 Series
(Continued)
Features
MB90V540
MB90F543/F549
MB90543/549
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (
× 1, × 2, × 3, × 4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL
× 4)
ROM
External
Boot-block
Flash memory 128 K/256 Kbytes
Mask ROM 128 K/256 Kbytes
RAM
8 Kbytes
6 Kbytes
Technology
0.5
m CMOS with on-
chip voltage regulator
for internal power supply
0.5
m CMOS with on-chip volt-
age regulator for internal power
supply + Flash memory On-chip
charge pump for programming
voltage
0.5
m CMOS with on-chip volt-
age regulator for internal power
supply
Operating
voltage range
5 V
±10 %
Temperature
range
40 to 85 °C
Package
PGA-256
QFP100
UART0
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500K/1M/2Mbps (synchronous) at System clock = 16 MHz
UART1(SCI)
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate: 1202/2404/4808/9615/31250 bps (asynchronous)
62.5K/12K/250K/500K/1 Mbps (synchronous) at 6,8,10,12,16 MHz
Serial IO
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate : 31.25K/62.5K/125K/500K/1Mbps at System clock = 16MHz
A/D Converter
10-bit or 8-bit resolution
8 input channels
Conversion time: 26.3
s (per one channel)
16-bit Reload
Timer
(2 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit IO Timer
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare(Channel 0)
Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys = System clock freq.)
16-bit
Output Compare
(4 channels)
Signals an interrupt when a match with 16-bit IO Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal