參數(shù)資料
型號(hào): MB89PV630C-SH
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封裝: CERAMIC, MDIP-64
文件頁數(shù): 86/153頁
文件大?。?/td> 7326K
代理商: MB89PV630C-SH
HARDWARE CONFIGURATION
2-15
(3) Description of registers
(a) STBC (Standby-conrol register)
[Bit 7] STP: Stop bit
Bit 7 specifies switching to the stop mode.
This bit is cleared at reset or stop cancellation.
0 is always read when this bit is read.
[Bit 6] SLP: Sleep bit
Bit 6 specifies switching to the sleep mode.
This bit is cleared at reset or stop cancellation.
0 is always read when this bit is read.
[Bit 5] SPL: Pin state specifying bit
Bit 5 specifies the external pin state in the watch or stop mode.
When the pins for which "Pull-up resistor provided" is specified in the mask option enter the stop mode
with SPL = 1, they are pulled up rather than having high impedance.
This bit is cleared at resetting.
[Bit 4] RST: Software reset bit
Bit 4 resets the software.
1 is always read when this bit is read.
If a software reset is performed during operation in a submode, one oscillation stabilization period is re
quired to switch to the main mode. Therefore, a reset signal is output during the oscillation stabilization
period.
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