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參數(shù)資料
| 型號： | MB89P195APF-201 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4.2 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 8.60 X 17.75 MM, 1.27 MM PITCH, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 66/256頁 |
| 文件大?。?/td> | 1811K |
| 代理商： | MB89P195APF-201 |
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8-10 Chapter 8 8-bit Serial I/O
MB89190/190A series
Table 8-4-1 Function of Each Bit of Serial Mode Register (SMR)
Bit name
Function
Bit 7
SIOF:
Interrupt request
flag bit
This bit is set to 1 when 8-bit serial data is input/output during serial I/O
operation. An interrupt request is output when this bit and the interrupt request
enable bit (SIOE) are 1.
When 0 is written to this bit, it is cleared.
When 1 is written to this bit, it is not affected and does not change.
Bit 6
SIOE:
Interrupt request
enable bit
Enables/disables interrupt request output to CPU. An interrupt request is output
when this bit and the interrupt request flag bit (SIOF) are 1.
Bit 5
SCKE:
Shift clock output
enable bit
Controls shift clock I/O
When this bit is 0, the P30/SCK pin functions as a shift clock input pin. When
this bit is 1, the P30/SCK pin functions as a shift clock output pin.
Note: To use the P30/SCK pin as the shift clock input, it must be set to the input
port. Select the external shift clock using the shift clock selection bit (CKS1,
CKS0 = 11B).
To use the pin as the shift clock output (SCKE = 1), select the internal shift
clock (CKS1, CKS0 = other than 11B).
Remark: When the shift clock output is enabled (SCKE = 1), the pin functions as a
SCK output pin irrespective of the state of the general-purpose port
(P30).
When using the pin as a general-purpose port (P30), set the pin as the
shift clock input (SCKE = 0).
Bit 4
SOE:
Serial data output
enable bit
When this bit is 0, the P31/SO pin functions as a general-purpose port (P31).
When this bit is 1, the pin functions as the serial data output pin (SO).
Remark: When the serial data output is enabled (SOE = 1), the pin functions as a
SO pin irrespective of the state of the general-purpose port (P31).
Bit 3
Bit 2
CKS1,CKS0:
Shift clock
selection bits
One shift clock is selected from three internal shift clocks and one external shift
clock.
When these bits are other than 11
B, an internal shift clock is selected; and if the
shift clock output enable bit (SCKE) is 1, the shift clock is output from the SCK
pin.
When these bits are 11
B, the external shift clock is selected; and if the pin is set
to the shift clock input, the shift clock is input from the SCK pin.
Bit 1
BDS:
Transfer direction
selection bit
Selects whether to transfer serial data starting at least significant bit (LSB first;
BDS = 0) or at most significant bit (MSB first; BDS = 1).
Note: When this bit is rewritten after writing data to the serial data register (SDR) to
change the places between the higher order and lower order of the data at
reading and writing to the SDR register, the data is invalid.
Bit 0
SST: Serial I/O
transfer start bit
Controls transfer start and transfer enable of serial I/O. This bit can also
determine the completion of the transfer.
When 1 is written to this bit when the internal shift clock is selected (CKS1, CKS0
= other than 11B), the shift clock counter is cleared and transfer is started.
When 1 is written to this bit when the external shift clock is selected (CKS1,
CKS0 = 11B), transfer is enabled, the shift clock counter is cleared, and the
external shift clock input wait state occurs.
When the transfer is completed, this bit is cleared to 0, and the SIOF bit is set to
1.
When 0 is written to this bit during transfer (SST = 1), transfer is suspended.
When transfer is suspended, it is necessary to reset the SDR register on the data
output side and resume the transfer on the data input side (clearing shift clock
counter).
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