參數(shù)資料
型號(hào)： MB89951PFM
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 0.65 MM PITCH, QFP-64
文件頁(yè)數(shù)： 79/110頁(yè)
文件大?。?/td> 619K
代理商： MB89951PFM
HARDWARE CONFIGURATION
2– 55
[When transfer suspended]
Note: When data is written at the SDR, the output data changes at the
falling edge of the external-clock pulse.
Fig. 2.19 Shift Start/Stop Timing
(e) Input/output shift timing
Data is output from the serial output pin (SO) at the falling edge of the shift-
clock pulse, and is input from the serial input pin (SI) to the SDR at the
rising edge of the shift-clock pulse.
a. LSB first (BDS = 0)
b. MSB first (BDS = 1)
Fig. 2.20 Input/Output Shift Timing
Peripherals
#0
#1
#2
#5
SCK
#3
#4
SO
SIOF
SST
#0
#1
#2
#5
#6
#7
SCK
#3
#4
SO
SI
#0
#1
#2
#5
#6
#7
#3
#4
SI input
SO output
#7
#6
#5
#2
#1
#0
SCK
#4
#3
SO
SI
SI input
SO output
#7
#6
#5
#2
#1
#0
#4
#3
DI7 to DI0 indicate input data, and DO7 to DO0 indicate output data.
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