參數(shù)資料
型號(hào)： MB89951PFM
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 0.65 MM PITCH, QFP-64
文件頁(yè)數(shù)： 49/110頁(yè)
文件大?。?/td> 619K
代理商： MB89951PFM
HARDWARE CONFIGURATION
2– 28
(4) Description of operation
(a) Timer function
Setting the P/TX bit of the CNTR to 0 gives the timer-operation mode. When
the TPE bit of the CNTR is set to 1, the counter starts incrementing from
00H. When the value of the counter agrees with that of the COMR, the
counter is cleared on the next count clock pulse and incrementing restarts.
Therefore, the TIR bits are set and the output pin is reversed (but, when
the TPE bit is 0, the output pin is fixed at Low level) in cycles of the count
clock pulses when 00
H is written at the COMR, or in cycles 256 times longer
than those of the count clock pulses when FF
H is written.
If the value of the COMR is rewritten in the timer-operation mode, it becomes
effective from the next cycle (when the value of the counter is 00
H, the value
of the COMR is transferred to the comparator latch).
Fig. 2.11 Timer Operation
If the TIE bit of the CNTR is set to 1, an interrupt occurs when the values
of the counter and COMR match. During interrupt processing, the TIR bit
is used as the interrupt flag. The TIR bit is set irrespective of the value of
the TIE bit. However, if the values of the counter and COMR match, the
TIR bit is set to 1 even after an interrupt is disabled.
Writing 0 at the TIR bit permits clearing of the interrupt source or the TIR
bit. When the Read Modify Write instruction is read, the TIR bit is set so
that 1 can always be read to prevent erroneous clearing.
By using P0 and P1 bit in CNTR, 1 out of 4 clock sources can be selected
for the counter.
Peripherals
Count-clock pulse
Value of COMR
TIR bit setting
P41/PWM
00
01
FF
00
FF
TPE
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