參數(shù)資料
型號： MB86832-80PFV-G
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176
文件頁數(shù)： 54/54頁
文件大?。?/td> 269K
代理商： MB86832-80PFV-G
MB86832
Fujitsu Microelectronics, Inc.
9
-BE0
-BE1
-BE2/ADR1
-BE3/ADR0
O
I/O
O
BYTE ENABLE: Indicates the valid byte during a write when 32-bit bus width is used. During reads, -BE<3:0> are asserted without regard to the
bus width. When 8-bit bus width is used, -BE2 and -BE3 are driven with ADR1 and ADR0, respectively. When 16-bit bus width is used,
-BE2 is driven with ADR1. -BE<3:0> are valid during the bus cycle period. During idle cycles, the output is undened. During bus grant, the byte
enables are high impedance, the DRAM controller may be enabled, and -BE2 becomes the ADR1 input if 16-bit bus width is used.
*Notation such as (D<31:24>) shows the data bus bits being used.
RDWR
I/O
READ/WRITE BUS TRANSACTION: This signal is low during write cycles and high during read cycles and idle cycles. It is an input
during bus grant mode, and it is used for generating -DWE0 and -DOE when the DRAM controller is enabled. This signal is not used in bus grant
mode when the DRAM controller is disabled.
-READY
I
EXTERNAL READY: This is a control signal asserted by the external memory system to indicate that the current bus transaction is being com-
pleted and that it is ready to start with the next bus transaction in the following cycle. In case of a fetch from memory, the processor will strobe the
value on the data bus at the rising edge of CLK_IN following the assertion of –READY. For the case of a write, the memory system will assert –
READY when the appropriate access time has been met.
In most cases, no additional logic is required to generate the –READY signal. On-chip circuitry can be programmed to assert –READY based on
the address of the current transaction. The external system can override the internal ready generator to terminate the current bus cycle early. -
READY must be pulsed an appropriate number of times during a burst transfer or when multiple bus cycles are required to transfer data with 8- or
16-bit bus width.
Table 3. Signal Descriptions (Continued)
Symbol
Type
Description
Bus Width
Access Type
-BE0,1,2,3
32-bit
Write
Byte 0 (D<31:24>) *1
0111
Byte 1 (D<23:16>)
1011
Byte 2 (D<15:8>)
1101
Byte 3 (D<7:0>)
1110
Half Word 0 (D<31:16>)
0011
Half Word 1 (D<15:0>)
1100
Word
0000
Read
All data types
0000
16-bit
Write
Byte 0 (D<15:8>)
1000
Byte 1 (D<7:0>)
0100
Byte 2 (D<15:8>)
1010
Byte 3 (D<7:0>)
0110
Half Word 0 (D<15:0>)
0000
Half Word 1 (D<15:0>)
0010
Word (D<15:0>) Access 0
0010
Word (D<15:0>) Access 1
0000
Read
Access 0
0000
Access 1
0010
8-bit
Write
Byte 0
XX00
Byte 1
XX01
Byte 2
XX10
Byte 3
XX11
Half Word 0 Access 0
XX11
Half Word 0 Access 1
XX10
Half Word 1 Access 0
XX01
Half Word 1 Access 1
XX00
Word Access 0
XX11
Word Access 1
XX10
Word Access 2
XX01
Word Access 3
XX00
Read
Access 0
XX00
Access 1
XX01
Access 2
XX10
Access 3
XX11
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