參數(shù)資料
型號(hào)： MB86832-80PFV-G
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176
封裝： 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176
文件頁(yè)數(shù)： 46/54頁(yè)
文件大?。?/td> 269K
代理商： MB86832-80PFV-G
SPARClite Series 32-Bit RISC Embedded Processor
50
Fujitsu Microelectronics, Inc.
AC Characteristics (continued)
Notes:
1.
The rst value is for 33 MHz bus operation, and the second value is for 40 MHz bus operation.
2.
In the absence of documentation to the contrary, all parameters are valid within the specied temperature and power supply ranges. These specications
are subject to change for performance improvement.
3.
All voltage values have the GND (VSS = 0V) as their reference. Timing measurement reference points are 1.5V, input level from 0.4V to 2.4V, and input
rise and fall times are 2ns or less.
4.
Do not short multiple output pins for more than 1 second. External output load capacity is 30 pF.
5.
Pins which are specied for asynchronous input, and standards other than -RDYOUT during external READY mode, are referenced from the external
clock (CLKIN) rising edge.
6.
-RDYOUT during external READY mode is referenced from the -READY input.
7.
A minimum of four CLKIN Cycles are required for reset initialization. Also, 4,000 CLKIN cycles are required for PLL oscillation stabilization time.
Figure 29.
Reset Timing
Figure 30.
Clock Timing
Symbol
Parameter Description
IO_VDD = 5V + 5%
IO_VDD = 3.3V + 0.3V
Units
Min.
Max.
Min.
Max.
IRQ<15:8> Input setup time
Asynchronous
ns
IRQ<15:8> Input hold time
Asynchronous
ns
IRQ<15:8> Input High level duration
2
P+10
-
2
P+10
-
ns
IRQ<15:8> Input Low level duration
2
P+10
-
2
P+10
-
ns
CLKIN
ADDR
-RESET
4 Cycle Minimum
0x0000 0000
*
1
*1. CLKIN must be stable before -RESET is deasserted.
*2. When -RESET hold time is met.
3 Cycles *2
t1
t5
t2
t3
t4
2.8v
0.8v
1.5v
CLKIN
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