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| 型號： | MB86832-80PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件頁數(shù)： | 53/54頁 |
| 文件大小： | 269K |
| 代理商： | MB86832-80PFV-G |
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SPARClite Series 32-Bit RISC Embedded Processor
8
Fujitsu Microelectronics, Inc.
Table 3. Signal Descriptions
Symbol
Type
Description
CLKIN
I
CLOCK: The clock input pin. The clock is the timebase for the operation of the bus interface unit (BIU). An on-chip clock multiplier allows the
CPU and core logic to run at integer multiples of the clock frequency (
1, 2, 3, 4, or 5).
CLKEXT
I
EXTERNAL CLOCK BYPASS: The external clock selection pin. If tied low, the clock is generated by the internal PLL/clock multiplier. If tied
high, the external clock (i.e., the signal on CLKIN) is used without modication.
-RESET
I
SYSTEM RESET: The reset input. The CPU and core logic are initialized by pulsing this input low. The clock must be stable for 100 ms before
the reset pulse is de-asserted. The reset pulse must be a minimum of four CLKIN cycles in length. The CPU begins execution at
location 0 three CLKIN cycles after the reset pulse is de-asserted.
CLKSEL0
CLKSEL1
CLKSEL2
I
INTERNAL CLOCK SELECT: These pins select the clock frequency multiplier, as described in the table below.
Note: CLKSEL0 and CLKSEL1 do not have internal pullup resistors, so they must be tied high or low. CLKSEL2 has an internal 50K
W pullup
resistor.
-CTEST
-BTEST
I
CTEST BTEST: Test pins. Must be tied high.
ADR<27:2>
I/O
ADDRESS BUS: The 26-bit address bus ADR<27:2> references a 32-bit word. ADR1 and ADR0 are generated for 8- and 16-bit bus width trans-
actions and are driven on the byte enables -BE2 and -BE3. The address is not valid during idle cycles. During bus grant mode, the address bus
becomes an input, and it is used by the -CS generator circuit and on-chip core logic. When ADR<27:2> is driven in this mode, ADR<31:28> are
treated as 0 internally. If the DRAM controller is enabled, it multiplexes row and column addresses and drives them on ADR<13:2>.
ASI<3:0>/
ADR<28:31>
I/O
ADDRESS SPACE IDENTIFIER: The address space identier (ASI) selects one of 16 separate address spaces referenced by the address bus.
These spaces distinguish between user and supervisor space, instruction and data space, memory and peripheral control registers, and other
addressable areas. When ASISEL is high these pins are ASI<3:0>, while when ASISEL is low these pins are ADR<28:31>. The timing is identical
to ADR<27:2>. The ASI signals become inputs during bus grant mode when ASISEL is taken low. This is used for CS generation and internal
address decoding. In this mode, ASI<7:4> is treated as 0 internally by the CPU and core logic.
ASISEL
I
ASI SELECT SIGNAL: In bus grant mode, used to select whether the signals on pins 112 through 115 drive ASI<3:0> or ADR<24:27>.
This pin has a pullup resistor.
-AS
I/O
ADDRESS STROBE: A one-cycle low pulse is driven on -AS during the rst clock of the bus cycle. The bus cycle starts with assertion of
-AS and ends with assertion of -READY or -RDYOUT. The -AS signal is an input during bus grant mode and is used as an activation signal for CS
generator circuits and wait-state generator circuits.
-CS0
-CS1
-CS2
-CS3
-CS4
-CS5
O
CHIP SELECT: The chip select signals are asserted if the address ranges indicated in the Address Range Specier Register (ARSR) and the
Address Mask Register (AMR) are referenced with the System Support Control Register (SSCR) CS enable bit (bit 4) set. An exception is
-CS0 (i.e. the boot ROM chip select), which has no Address Range Specier Register and is always enabled. Each address range has a corre-
sponding wait specier which is used to automatically assert the –READY signal after a user dened number of processor clocks. This allows a
variety of memory and I/O devices with different access times to be connected to the processor without the need for additional logic.
D<31:0>
I/O
DATA BUS: This is the 32-bit data bus. It is a bidirectional data bus used for instruction fetch, data reads, and data writes. Instruction and word
data must be aligned to 32-bit boundaries, and half words must be aligned to even addresses. Double words must be aligned to addresses which
are multiples of 8. In 8-bit bus mode D<7:0> is used, and in 16-bit bus mode D<15:0> is used.
CLKSEL2
CLKSEL1
CLKSEL0
Internal Clock
H
L
x1
H
L
H
x2
H
L
x3
H
x4
L
H
x5
ASISEL
ASI<3:0> / ADR <28:31>
L
ADR <28:31>
H
ASI <3:0>
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86833 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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