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參數(shù)資料
| 型號： | MB81V4800S-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 512K×8 BIT Fast Page Mode DRAM(CMOS 512K×8位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS為512k × 8位快速頁面模式的DRAM（的CMOS為512k × 8位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 4/26頁 |
| 文件大小： | 328K |
| 代理商： | MB81V4800S-60 |
4
MB81V4800S-60/MB81V4800S-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Nineteen input bits are required to decode any eight of 4,194,304 cell addresses in the memory matrix. Since only
ten address bits are available, the column and row inputs are separately strobed by CAS and RAS as shown in
Figure 5. First, ten row address bits are input on pins A
0
-through-A
9
and latched with the row address strobe (RAS)
then, nine column address bits are input on pins A
0
-through-A
8
and latched with the column address strobe (CAS).
Both row and column addresses must be stable on or before the falling edge of CAS and RAS, respectively. The
address latches are the flow-through type; thus, address information appearing after t
RAH
(min.) + t
T
is automatically
treated as the column address to start select operation of the column decode. Therefore, to have correct data within
t
RAC
, the column address should be input within t
RAD
(max.). If t
RAD
> t
RAD
(max.), the access time is the later one of
either t
AA
or t
CAS
.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data are ignored. When an early write cycle
is executed, the output buffers stay in a high-impedance state during the cycle.
DATA INPUT
Input data are written into memory in either of three basic ways—the early write cycle, the OE (delayed) write cycle,
and the read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In the early write cycle, the input data (DQ
1
-DQ
8
) are strobed by CAS and the setup/hold times are referenced
to falling edge of CAS because WE goes Low before CAS. In the delayed write or read-modify-write cycle, WE
goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the falling edge
of WE. Since this device is an I/O common type, when the delayed write or read-modified-write is executed, I/O
data have to be controlled by OE.
DATA OUTPUT
The three-state buffers are LVTTL compatible with a fanout of one TTL load. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max.) is satisfied.
t
CAC
:
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max.).
t
AA
:
from column address input when t
RAD
is greater than t
RAD
(max.).
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the
output buffers remain in a high-impedance state during the entire cycle.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp
Supply Voltage
V
CC
3.0
3.3
3.6
V
0
°
C to +70
°
C
V
SS
0
0
0
Input High Voltage, all inputs
V
IH
2.0
—
V
CC
+0.3
V
Input Low Voltage, all inputs(*)
V
IL
–0.3
—
0.8
V
Input Low Voltage, DQ(*)
V
ILD
–0.3
—
0.8
V
1
1
1
1
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