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參數(shù)資料
| 型號(hào)： | MB81N643289 |
| 廠商： | Fujitsu Limited |
| 英文描述： | DRILL BIT HIGH SPEED STEEL .021,1 |
| 中文描述： | 8 × 256K × 32位的雙倍數(shù)據(jù)速率FCRAMTM |
| 文件頁數(shù)： | 19/64頁 |
| 文件大小： | 1732K |
| 代理商： | MB81N643289 |
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19
MB81N643289-50/-60
Preliminary (AE1E)
I
FUNCTIONAL DESCRIPTION
DDR, Double Data Rate Function
The regular SDRAM read and write cycle have only used the rising edge of external clock input. When clock signal
goes to High from Low at the read mode, the read out data will be available at every rising clock edge after the
specified latency up to burst length. The MB81N643289 DDR FCRAM features a twice of data transfer rate within
a same clock period by transferring data at every rising and falling clock edge. Refer to Figure 3 in Page 24.
FCRAM
TM
The MB81N643289 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
CLOCK (CLK, CLK)
The MB81N643289 adopts differential clock scheme. CLK is a master clock and its rising edge is used to latch all
command and address inputs. CLK is a complementary clock input.
The MB81N643289 implements Delay Locked Loop (DLL) circuit. This internal DLL tracks the signal cross point
between CLK and CLK and generate some clock cycle delay for the output buffer control at Read mode.
The internal DLL circuit requires some Lock-on time for the stable delay time generation. In order to stabilize the
delay, a constant stable clock input for l
LOCK
period is required during the Power-up initialization and a constant stable
clock input for l
LOCK
period is also required after Self-refresh exit as specified l
LOCK
prior to the any command.
POWER DOWN (PD)
PD is a synchronous input signal and enables power down mode.
When all banks are in idle state, PD controls Power Down (PD) and Self-refresh mode. The PD and Self-refresh is
entered when PD is brought to Low and exited when it returns to High.
During the Power Down and Self-refresh mode, both CLK and CLK are disabled after specified time.
PD does not have a Clock Suspend function unlike CKE pin of regular SDRAMs, and it is illegal to bring PD into
Low if any read or write operation is being performed. For the detail, refer to Timing Diagrams.
It is recommended to maintain PD to be Low until V
DD
gets in the specified operating range in order to assure the
power-up initialization.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, all command signals
are negated but internal operation such as burst cycle will not be suspended.
COMMAND INPUTS (RAS, CAS and WE)
As well as regular SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a rising
edge of the CLK determines FCRAM operation. Refer to FUNCTION TRUTH TABLE in page 5.
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