參數(shù)資料
型號: MB814405D-70
廠商: Fujitsu Limited
英文描述: 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動(dòng)態(tài)RAM)
中文描述: 100萬× 4位超頁模式動(dòng)態(tài)RAM的CMOS(100萬× 4位超級頁面存取模式動(dòng)態(tài)內(nèi)存)
文件頁數(shù): 19/29頁
文件大?。?/td> 596K
代理商: MB814405D-70
19
MB814405D-60/60L/-70/70L
t
HPC
Fig. 12 – HYPER PAGE MODE EARLY WRITE CYCLE
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
WE
DQ
(Input)
A
0
to A
9
V
OH
V
OL
DQ
(Output)
DESCRIPTION
The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except WE is set to a
low state and OE is a “H” or “L” signal. Data appearing on the DQ pins is latched on the falling edge of CAS and the data is written
into the memory. During the hyper page mode write cycle, including the delayed (OE) write and read-modify-write cycles, t
CWL
must
be satisfied.
“H” or “L”
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
t
CAS
t
RASP
t
CRP
t
RP
ROW
ADD
t
RSH
t
RCD
t
CSH
t
CAS
t
ASC
t
CAH
t
ASR
COL
ADD
COL
ADD
HIGH-Z
t
CAS
t
CP
COL
ADD
t
CAH
t
RAL
t
ASC
t
CAH
VALID
DATA
VALID
DATA
t
WCS
t
WCH
t
WCS
t
WCH
t
WCS
t
WCH
t
DS
t
DH
t
ASC
t
RAH
t
DS
t
DH
t
DS
t
DH
t
AR
t
WCR
t
DHR
t
RHPC
t
CWL
t
CWL
t
CWL
t
RWL
VALID
DATA
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