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參數(shù)資料
| 型號： | MB814400A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 1位快速頁面模式的DRAM的CMOS（4分× 1位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 347K |
| 代理商： | MB814400A-70 |
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MB814400A-60/MB814400A-70/MB814400A-80
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality
of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle. CAS makes a transition from High to Low while RAS
is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
9
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
9
are defined by latching levels on A
0
-A
9
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 1024 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated by the internal
refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
Fig. 17 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
V
IH
V
IL
V
IH
V
IL
RAS
CAS
A
0
to A
9
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Output)
OE
“H” or “L”
Valid Data
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
VALID DATA IN
COLUMN ADDRESS
Parameter
Unit
Min.
—
Max.
55
—
—
Min.
—
Max.
60
—
—
ns
No.
Min.
—
Max.
50
—
—
90
(At recommended operating conditions unless otherwise noted.)
MB814400A-60 MB814400A-70
Note . Assumes that CAS-before-RAS refresh counter test cycle only.
Symbol
91
92
30
80
35
90
ns
ns
30
75
Column Address Hold Time
CAS to WE Delay Time
93
94
CAS Pulse Width
RAS Hold Time
55
60
—
—
ns
—
50
55
60
—
—
ns
—
50
MB814400A-80
Access Time from CAS
t
CHR
DQ
(Input)
t
CSR
t
CP
t
FRSH
t
FCAS
t
RP
t
RAL
t
FCAH
t
ASC
t
WSR
t
WHR
t
RCS
t
FCWD
t
CWL
t
RWL
t
WP
t
DH
t
DS
t
DZC
t
OED
t
FCAC
t
OEZ
t
OEA
t
ON
t
DZO
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB814400A-80 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4M ×1 位快速頁面存取模式動態(tài)RAM) |
| MB814400C-60 | CMOS 1 M ×4BIT Fast Page Mode DRAM(CMOS 1 M ×4 位快速頁面存取模式動態(tài)RAM) |
| MB814400C-70 | CMOS 1 M ×4 BIT Fast Page Mode DRAM(CMOS 1 M ×4 位快速頁面存取模式動態(tài)RAM) |
| MB814400D-60 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動態(tài)RAM) |
| MB814400D-70 | CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB814400C-70PJN | 制造商:FUJITSU 功能描述:Dynamic RAM, Fast Page, 1M x 4, 26 Pin, Plastic, SOJ |
| MB814405D-60PJN | 制造商:FUJITSU Component Ltd 功能描述: |
| MB8146112 | 制造商:FUJITSU 功能描述:* |
| MB81461-12PSZ | 制造商:FUJITSU 功能描述:VRAM, FAST PAGE, 64KX4, 24 Pin, Plastic, ZIP |
| MB81461B-12 | 制造商:FUJITSU 功能描述: 制造商:FUGITSU 功能描述:81461B-12 制造商:FUJITSU 功能描述:81461B-12 |
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