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| 型號： | MB8117400A-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 4位快速頁面模式的DRAM（的CMOS 4米× 4位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 11/27頁 |
| 文件大小： | 304K |
| 代理商： | MB8117400A-60 |
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11
MB8117400A-50/MB8117400A-60/MB8117400A-70
Notes: 1. Referenced to V
SS
.
2. I
CC
depends on the output load conditions and cycle rates; The specified values are obtained with the
output open. I
CC
depends on the number of address change as RAS= V
IL
, CAS= V
IH
and V
IL
> –0.3V.
I
CC1
, I
CC3
, I
CC4
and I
CC5
are specified at one time of address change during RAS= V
IL
and CAS= V
IH
. I
CC2
is specified during RAS=V
IH
and V
IL
>–0.3V.
3. An initial pause (RAS=CAS=V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only
cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum
of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
4. AC characteristics assume t
T
= 5ns.
5. V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Also transition times
are measured between V
IH
(min.) and V
IL
(max.).
6. Assumes that t
RCD
≤
t
RCD
(max.), t
RAD
≤
t
RAD
(max.). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown. Refer
to Fig. 2 and 3.
7. If t
RCD
≥
t
RCD
(max.), t
RAD
≥
t
RAD
(max.), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
8. If t
RAD
≥
t
RAD
(max.) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
9. Measured with a load equivalent to two TTL loads and 100 pF.
10. t
OFF
and t
OEZ
is specified that output buffer change to high impedance state.
11. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. t
RCD
(min.) = t
RAH
(min.)+ 2t
T
+ t
ASC
(min.).
13. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
15. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min.) the data output pin will remain High-Z
state through entire cycle.
16. Assumes that t
WCS
< t
WCS
(min.).
17. Either t
DZC
or t
DZO
must be satisfied.
18. t
CPA
is access time from the selection of a new column address (that is caused by changing CAS from
“L” to “H”). Therefore, if t
CP
is long, t
CPA
is longer than t
CPA
(max.).
19. Assumes that CAS-before-RAS refresh.
20. t
WCS
, t
CWD
, t
RWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet
as an electrical characteristic only. If t
WCS
> t
WCS
(min.), the cycle is an early write cycle and Dout pin
will maintain high impedance state thoughout the entire cycle. If t
CWD
> t
CWD
(min.), t
RWD
> t
RWD
(min.),
and t
AWD
> t
AWD
(min.), the cycle is a read modify-write cycle and data from the selected cell will appear
at the Dout pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and
invalid data will appear the Dout pin , and write operation can be executed by satisfying t
RWL
, t
CWL
, and
t
RAL
specifications.
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