參數(shù)資料
型號(hào)： MB8116405A-70
廠商： Fujitsu Limited
英文描述： CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS（4米× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 536K
代理商： MB8116405A-70
5
MB8116405A-60/MB8116405A-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. Since
only twelve address bits (A
0
to A
11
) are available, the row and column inputs are separately strobed by RAS and
CAS as shown in Figure 1. First, twelve row address bits are input on pins A
address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS).
Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The
address latches are of the flow-through type; thus, address information appearing after t
treated as the column address.
WRITE ENABLE
0
-through-A
11
and latched with the row
RAH
(min.)+ tT is automatically
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
to DQ
4
) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS ; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to
that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low.
When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the following
conditions:
t
RAC
:
t
CAC
:
t
AA
:
t
OEA
:
t
OEZ
:
t
OFF
:
t
OFR
:
t
WEZ
:
from the falling edge of RAS when t
RCD
(max.) is satisfied.
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max.).
from column address input when t
RAD
is greater than t
RAD
(max.), and t
RCD
(max.) is satisfied.
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
from OE inactive.
from CAS inactive while RAS inactive.
from RAS inactive while CAS inactive.
from WE active while CAS inactive.
The data remains valid after either OE is inactive, or both RAS and CAS are inactive, or CAS is reactived. When
an early write is execute, the output buffers remain in a high-impedance state during the entire cycle.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp.
Supply Voltage
V
CC
V
SS
4.5
0
5.0
0
5.5
0
V
0
°
C to +70
°
C
Input High Voltage, All Inputs
V
IH
2.4
—
6.5
V
Input Low Voltage, All Inputs/Outputs*
V
IL
–0.3
—
0.8
V
1
1
1
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