參數(shù)資料
型號: MB673xxx
廠商: Fujitsu Limited
英文描述: CMOS Gate Array
中文描述: CMOS門陣列
文件頁數(shù): 91/106頁
文件大?。?/td> 1648K
代理商: MB673XXX
MB90670/675 Series
91
(10) UART0 Timing
(AV
CC
= V
CC
= 2.7 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
Min.
8 t
CP
*
V
CC
= 5.0 V
±
10%
– 80
V
CC
= 3.0 V
±
10%
– 120
V
CC
= 5.0 V
±
10%
100
V
CC
= 3.0 V
±
10%
200
* : For t
CP
(internal operating clock cycle time), refer to “(3) Clock Timing”.
Notes :
These are AC ratings in the CLK synchronous mode.
C
L
is the load capacitor connected to pins while testing.
Parameter
Symbol Pin name
Condition
Unit
Remarks
Max.
80
120
Serial clock cycle time
SCK
↓ →
SOT delay
time
t
SCYC
t
SLOV
t
SLOV
t
IVSH
t
IVSH
ns
ns
ns
ns
ns
Internal shift
clock mode
C
L
= 80 pF
+ 1 TTL for an
output pin
Valid SIN
SCK
SCK
↑ →
valid SIN hold
time
Serial clock “H” pulse
width
Serial clock “L” pulse
width
SCK
↓ →
SOT delay
time
t
SHIX
1 t
CP
*
ns
t
SHSL
4 t
CP
*
ns
External shift
clock mode
C
L
= 80 pF
+ 1 TTL for an
output pin
t
SLSH
4 t
CP
*
ns
t
SLOV
t
SLOV
t
IVSH
t
IVSH
t
SHIX
t
SHIX
V
CC
= 5.0 V
±
10%
V
CC
= 3.0 V
±
10%
V
CC
= 5.0 V
±
10%
V
CC
= 3.0 V
±
10%
V
CC
= 5.0 V
±
10%
V
CC
= 3.0 V
±
10%
60
120
60
120
150
200
ns
ns
ns
ns
ns
ns
Valid SIN
SCK
SCK
↑ →
valid SIN hold
time
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