參數(shù)資料
型號: MB673xxx
廠商: Fujitsu Limited
英文描述: CMOS Gate Array
中文描述: CMOS門陣列
文件頁數(shù): 69/106頁
文件大?。?/td> 1648K
代理商: MB673XXX
MB90670/675 Series
69
14. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime
operating system (REALOS software). The module can be used to generate hardware interrupt requests to the
CPU with software and cancel the interrupt requests.
This module does not conform to the extended intelligent I/O service (EI
2
OS).
(1) Register Configuration
(2) Block Diagram
Delayed interrupt factor generation/cancellation register (DIRR)
Address
bit 15
bit 14
bit 13
00009F
H
bit 7 . . . . . . . . . . . .
R0
bit 12
bit 11
bit 10
bit 9
bit 8
(Reserved area)
R/W
Initial value
- - - - - - - 0
B
R/W : Readable and writable
— : Unused
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt signal
S factor
R0
Internal data bus
Interrupt request signal
#42 (2A
H
)*
R latch
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