參數(shù)資料
型號(hào)： MB673xxx
廠商： Fujitsu Limited
英文描述： CMOS Gate Array
中文描述： CMOS門(mén)陣列
文件頁(yè)數(shù)： 60/106頁(yè)
文件大?。?/td> 1648K
代理商： MB673XXX
MB90670/675 Series
60
9.
I
2
C Interface (Included Only in MB90675 Series)
The I
2
C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I
2
C bus and
has the following features.
Master/slave transmission/reception
Arbitration function
Clock synchronization function
Slave address/general call address detection function
Transmission direction detection function
Repeated generation function start condition and detection function
Bus error detection function
(1) Register Configuration
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
I
2
C bus status register (IBSR)
bit 15
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(IBCR)
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 0
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
(IBSR)
Initial value
00000000
B
Address
000040
H
Address
000041
H
Initial value
00000000
B
bit 15
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(IADR)
—
—
R/W
—
—
EN
CS4
CS3
CS2
CS1
CS0
Initial value
--0XXXXX
B
Address
000042
H
R/W
R/W
R/W
R/W
R/W
I
2
C bus control register (IBCR)
I
2
C bus clock control register (ICCR)
—
A6
A5
A4
A3
A2
A1
A0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(ICCR)
Address
000043
H
(IADR)
Initial value
-XXXXXXX
B
bit 15
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(Reserved area)
D7
Initial value
XXXXXXXX
B
Address
000044
H
(IDAR)
R/W
R/W
R/W
R/W
R/W
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
:
Readable and writable
:
Read only
:
Unused
:
Indeterminate
R/W
R
—
X
I
2
C address register (IADR)
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