參數(shù)資料
型號(hào)： MB582A
廠商： Fujitsu Limited
英文描述： 155-Mbps ATM Transceiver(155Mbps 異步傳輸模式 收發(fā)器)
中文描述： 155 - Mbps的自動(dòng)柜員機(jī)收發(fā)器（155Mbps異步傳輸模式收發(fā)器）
文件頁(yè)數(shù)： 8/46頁(yè)
文件大小： 345K
代理商： MB582A
8
MB582A/583A
MB583A (Receiver)
(Continued)
Pin no.
Symbol
Pin name
I/O interface
(speed)
Function
41
39
D
D
Serial data
input
PECL input
<155.52
Mbps>
Serial data input pins:
coded data at 155.52 Mbps.
These pins input NRZ-
45
44
LOSI
LOSI
Loss input
PECL input
<0 or 1>
Loss input pins:
the input serial data is regarded as being lost; the
RX-READY and LOSO pins output Low- and High-
level signals, respectively. Since the LOSI and
LOSI pins are both connected to the reference
voltage via an internal high resistor, single input is
allowed with either of the pins open. These pins are
used when TLOSI = GND.
When LOSI = “1” and LOSI = “0,”
43
TLOSI
Loss input
TTL input
<0 or 1>
Loss input pin:
serial data is regarded as being lost; the LOSO pin
outputs the High-level signal. This pin is used when
LOSI = GND and LOSI = Open.
When this pin inputs “1,” the input
46
REFCLK
Reference
clock input
TTL input
<19.44 or
51.84 MHz>
Reference clock input pin:
PLL circuit in the clock recovery unit. Connect a
stable oscillator (such as a crystal oscillator within
±
20 ppm) to this pin.
One of two reference clocks can be selected.
This pin is used for the
6
REFSEL
Reference
clock
selection
TTL input
<0 or 1>
Reference clock selection pin:
The 19.44- and 51.84-MHz reference clocks are
selected when this pin inputs “1” and “0,”
respectively.
30
EXTCLK
External
clock input
PECL input
<up to
155.52 MHz>
Single PECL input pin:
frequency external clock signal to execute an 1-to-8
demultiplexer function independent of the clock
recovery unit.
In this case, the operating frequency is free and may
be up to 155.52 MHz. This pin is used when
CLKSEL = “0”.
This pin inputs a high-
34
CLKSEL
Clock
selection
TTL input
<0 or 1>
Clock selection pin:
The clock generated by the clock recovery unit and
the EXTCLK clock are selected when this pin inputs
“1” and “0,” respectively.
33
RESET
Reset input
TTL input
<0 or 1>
Asynchronous reset input pin:
initialize the internal state. The internal circuit is
reset when this pin inputs “0”.
Upon reset, the RX-READY, POCLK, and DO0 to
DO7 pins output Low-level signals.
The device must be reset when the power is turned
on. For details, see “POWER-ON RESET,P17.”
This pin is used to
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