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參數(shù)資料
| 型號： | MB582A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 155-Mbps ATM Transceiver(155Mbps 異步傳輸模式 收發(fā)器) |
| 中文描述： | 155 - Mbps的自動柜員機收發(fā)器（155Mbps異步傳輸模式收發(fā)器） |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 345K |
| 代理商： | MB582A |
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MB582A/583A
(2) Connect a 4.7
resetting the sleep mode.
Be sure that the PDOWN signal has an active phase of at least 500 ms. (See the diagram below.)
This method allows the RESET signal to be used without considering the restrictions described in method (1).
The RESET pin may be left open.
Note, however, that a stable reference clock signal (REFCLK or PICLK) must be input within 50 ms after the
power save mode is canceled (as shown in the following illustration.)
μ
F external capacitor between the TIMER and GND pins. The capacitor is used for automatically
Using the MB583A Sleep Mode
It is necessary to use method (1) when using the sleep mode, otherwise the device will not return to normal operating
status.
(1) Apply a reset to the device when the LOSO output goes high (the LOS state detected), then cancel the reset
50 ms after the LOSO output goes low (receive state) or input a reset pulse with a width of 50 ms after the
LOSO output changes from high to low. Note that a stable reference clock signal (REFCLK) must be input
before the reset is canceled. (See the diagram below.)
Be sure to leave the TIMER pin open when not in use.
(active)
(inactive)
PDOWN
500 ms or more
Within
50 ms
Stable reference clock
Reference clock
50 ms or more
50 ms or more
(active)
(inactive)
(inactive)
(active)
(inactive)
Select
either
RESET
RESET
(active)
LOSO
Stable reference clock
Reference clock
Stable reference clock
Reference clock
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