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參數(shù)資料
| 型號： | MB15F73ULPVA |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2250 MHz, PBCC20 |
| 封裝： | PLASTIC, BCC-20 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大小： | 152K |
| 代理商： | MB15F73ULPVA |
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MB15F73UL
8
I
FUNCTIONAL DESCRIPTION
1.
Pulse swallow function
f
VCO
=
[ (P
×
N)
+
A]
×
f
OSC
÷
R
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
P
: Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64or 128 for RF-PLL)
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0
≤
A
≤
127, A < N)
f
OSC
: Reference oscillation frequency (OSC
IN
input frequency)
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2.
Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-
PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
(1)
Shift Register Configuration
The programmable
reference counter
for the IF-PLL
The programmable
reference counter
for the RF-PLL
The programmable
counter and the swallow
counter for the IF-PLL
The programmable
counter and the swallow
counter for the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
Programmable Reference Counter
CS
R1 to R14
T1, 2
CN1, 2
X
: Charge pump current select bit
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)
: LD/fout output setting bit
: Control bit
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
18
19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
X
X
X
(LSB)
(MSB)
Data Flow
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| MB15F73UV | Dual Serial Input PLL Frequency Synthesizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F73ULPVA-GE1 | 功能描述:IC SYNTHESIZR PLL DL INP 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| MB15F73UV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F73UVPVB | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F74UL | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F74ULPVA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
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