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參數(shù)資料
| 型號(hào)： | MB15F08SL |
| 廠商： | Fujitsu Limited |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | 雙串行輸入鎖相環(huán)頻率合成器 |
| 文件頁(yè)數(shù)： | 9/27頁(yè) |
| 文件大?。?/td> | 239K |
| 代理商： | MB15F08SL |
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9
MB15F08SL
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Note:
Divide ratio less than 3 is prohibited.
Table.3 Test Purpose Bit Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
16383
T
1
T
2
LD/fout pin state
L
L
Outputs fr
TX
H
L
Outputs fr
RX
L
H
Outputs fp
TX
H
H
Outputs fp
RX
Programmable Counter
LSB
MSB
Data Flow
CNT1, 2 : Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SW
TX/RX
: Divide ratio setting bits for the prescaler
(16/17 or 32/33 for the SW
TX
, 32/33 or 64/65 for the SW
RX
)
FC
TX/RX
: Phase control bit for the phase detector (TX: FC
TX
, RX: FC
RX
)
LDS
: LD/fout signal select bit
NOTE:
Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
L
D
S
S
W
RX
F
C
RX
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
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