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參數(shù)資料
| 型號(hào)： | MB15F08SL |
| 廠商： | Fujitsu Limited |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | 雙串行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MB15F08SL |
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3
MB15F08SL
I
PIN DESCRIPTION
Pin no.
Pin
name
I/O
Descriptions
SSOP
BCC
1
16
GND
RX
–
Ground for RX-PLL section.
2
1
OSC
IN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GND
TX
–
Ground for the TX-PLL section.
4
3
fin
TX
I
Prescaler input pin for the TX-PLL.
Connection to an external VCO should be via AC coupling.
5
4
V
CCTX
–
Power supply voltage input pin for the TX-PLL section.
6
5
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
7
6
PS
TX
I
Power saving mode control for the TX-PLL section. This pin must be set at
“L” during Power-ON. (Open is prohibited.)
PS
TX
= “H” ; Normal mode
PS
TX
= “L” ; Power saving mode
8
7
Do
TX
O
Charge pump output for the TX-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
9
8
Do
RX
O
Charge pump output for the RX-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
10
9
PS
RX
I
Power saving mode control for the RX-PLL section. This pin must be set at
“L” during Power-ON. (Open is prohibited.)
PS
RX
= “H” ; Normal mode
PS
RX
= “L” ; Power saving mode
11
10
Xfin
RX
I
Prescaler complementary input for the RX-PLL section.
This pin should be grounded via a capacitor.
12
11
V
CCRX
–
Power supply voltage input pin for the RX-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RX-PLL
is lost.
13
12
fin
RX
I
Prescaler input pin for the RX-PLL.
Connection to an external VCO should be via AC coupling.
14
13
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
14
Data
I
Serial data input (with a schmitt trigger input buffer.)
A data is transferred to the corresponding latch (TX-ref counter, TX-prog.
counter, RX-ref. counter, RX-prog. counter) according to the control bit in
the serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
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相關(guān)代理商/技術(shù)參數(shù) |
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