參數(shù)資料
型號: MB15F08SL
廠商: Fujitsu Limited
英文描述: Dual Serial Input PLL Frequency Synthesizer
中文描述: 雙串行輸入鎖相環(huán)頻率合成器
文件頁數(shù): 8/27頁
文件大?。?/td> 239K
代理商: MB15F08SL
8
MB15F08SL
I
FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation:
f
VCO
= [(M
×
N) + A]
×
f
OSC
÷
R (A < N)
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
M
: Preset divide ratio of dual modulus prescaler (16or 32 for TX-PLL, 32 or 64 for RX-PLL)
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0
A
127)
f
OSC
: Reference oscillation frequency
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX-PLL
sections, programmable reference dividers of TX/RX-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table.1 Control Bit
Shift Register Configuration
Control bit
Destination of serial data
CN1
CN2
L
L
The programmable reference counter for the TX-PLL
H
L
The programmable reference counter for the RX-PLL
L
H
The programmable counter and the swallow counter for the TX-PLL
H
H
The programmable counter and the swallow counter for the RX-PLL
Programmable Reference Counter
MSB
Data Flow
CN1,2
R1 to R14
T1, 2
CS
X
: Control bit
: Divide ratio setting bit for the programmable reference counter (5 to 16,383)[Table. 2]
: Test purpose bit
: Charge pump currnet select bit
: Dummy bits (Set “0” or “1”)
[Table. 1]
[Table. 3]
[Table. 9]
NOTE
: Data input with MSB first.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
C
S
X
X
X
X
LSB
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