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參數(shù)資料
| 型號(hào)： | MB15F07SLPV1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | XO, clock |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PBCC16 |
| 封裝： | PLASTIC, BCC-16 |
| 文件頁(yè)數(shù)： | 9/27頁(yè) |
| 文件大?。?/td> | 244K |
| 代理商： | MB15F07SLPV1 |
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9
MB15F07SL
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Note: Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
Divide ratio
(R)
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
16383
T1
T2
LD/fout pin state
L
L
Outputs fr
1
.
H
L
Outputs fr
2
.
L
H
Outputs fp
1
.
H
H
Outputs fp
2
.
Programmable Counter
LSB
MSB
Data Flow
CN1, CN2: Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SW
1
/
SW
2
: Divide ratio setting bit for the prescaler
(PLL 1 for the SW
1
, PLL 2 for the SW
2
)
FC
1
/
FC
2
: Phase control bit for the phase detector (PLL 1: FC
1
, PLL 2: FC
2
)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table 1]
[Table 4]
[Table 5]
[Table 6]
[Table 7]
[Table 8]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
L
D
S
S
W
1/2
F
C
1/2
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
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