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參數(shù)資料
| 型號： | MAXQ7670ATL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU W/10BIT ADC 40TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MAXQ® |
| 核心處理器： | RISC |
| 芯體尺寸： | 16-位 |
| 速度： | 16MHz |
| 連通性： | CAN，SPI |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 7 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.25 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________
15
Pin Description (continued)
PIN
NAME
FUNCTION
23
SCLK
SPI Serial Clock. SCLK is the SPI interface serial clock I/O. In SPI master mode, SCLK is an output. While in
SPI slave mode, SCLK is an input.
24
MOSI
SPI Serial Data I/O. MOSI is the SPI interface serial data output in master mode or serial data input in slave
mode.
25
MISO
SPI Serial Data I/O. MISO is the SPI interface serial data input in master mode or serial data output in slave
mode.
26
REGEN2
Active-Low +2.5V Linear Regulator Enable Input. Connect
REGEN2 to GNDIO to enable the +2.5V linear
regulator. Connect to DVDDIO to disable the +2.5V linear regulator.
27
TDO
JTAG Serial Test Data Output. TDO is the JTAG serial test, data output.
28
TMS
JTAG Test Mode Select. TMS is the JTAG test mode, select input.
29
TDI
JTAG Serial Test Data Input. TDI is the JTAG serial test, data input.
30
TCK
JTAG Serial Test Clock Input. TCK is the JTAG serial test, clock input.
31
P0.4/
ADCCNV
Port 0 Bit 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wake-up
capability. ADCCNV is a firmware-configurable, rising or falling edge, start/convert signal used to trigger
ADC conversions. The alternative function, ADCCNV, is selected using the register bits ACNT[2:0]. When
using ADCCNV as a trigger for ADC conversion, set P0.4/ADCCNV as an input using the PD0 register. This
action prevents any unintentional interference in the SARADC operation.
32
P0.5
Port 0 Bit 5. P0.5 is a general-purpose digital I/O with interrupt/wake-up capability.
33
RESET
Reset Input/Output. Active-low input/output with internal 55k
pullup to DVDDIO. Drive low to reset the
MAXQ7670. The MAXQ20 C core holds
RESET low during POR and during DVDD brownout conditions.
34
DGND
Digital Ground
35
XOUT
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation, or leave
unconnected if XIN is driven with an external clock source. Leave unconnected if an external clock source
is not used.
36
XIN
High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for normal operation,
or drive XIN with an external clock source. Leave unconnected if an external clock source is not used.
37
DVDD
Digital Supply Voltage. DVDD supplies internal digital core and flash memory. DVDD is directly connected to
the output of the internal +2.5V linear regulator. Disable the internal regulator (through
REGEN2) to connect an
external supply. Bypass DVDD to DGND with a 0.1F capacitor as close as possible to the device.
40
AVDD
Analog Supply Voltage. AVDD supplies PGA and ADC. AVDD is directly connected to the output of the
internal +3.3V linear regulator. Disable the internal regulator (via software) to connect an external supply.
Bypass AVDD to AGND with a 0.1F capacitor as close as possible to the device.
—
EP
Exposed Pad. Connect EP to the ground plane.
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