參數(shù)資料
型號: MAXQ7666BATM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, QCC48
封裝: 7 X 7 MM, ROHS COMPLAINT, TQFN-48
文件頁數(shù): 27/49頁
文件大小: 2130K
代理商: MAXQ7666BATM+
MAXQ7666
16-Bit, RISC, Microcontroller-Based,
Smart Data-Acquisition System
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33
MAXQ Core Architecture
The MAXQ7666 is structured on a highly advanced,
accumulator-based, 16-bit RISC architecture. Fetch and
execution operations complete in one cycle without
pipelining, because the instruction contains both the
operation code and data. The result is a streamlined 8
million instructions-per-second (MIPS) C.
A 16-level hardware stack supports the highly efficient
core, enabling fast subroutine calling and task switch-
ing. Manipulate data quickly and efficiently with three
internal data pointers. Multiple data pointers allow more
than one function to access data memory without hav-
ing to save and restore data pointers each time. The
data pointers automatically increment or decrement fol-
lowing an operation, eliminating the need for software
intervention. As a result, application speed is greatly
increased.
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The highly orthogonal instruction set allows arith-
metic and logical operations to use any register along
with the accumulator. Special-function registers (also
called peripheral registers) control the peripherals and
are subdivided into register modules.
The architecture is transport-triggered. Writes or reads from
certain register locations potentially cause side effects.
These side effects form the basis for the higher level opera-
tion codes defined by the assembler, such as ADDC, OR,
JUMP, etc. The operation codes are implemented as MOVE
instructions between certain register locations, while the
assembler handles the encoding.
Memory Organization
The MAXQ7666 incorporates several memory areas:
8KB (4K x 16) utility ROM
16KB (8K x 16) program flash memory for program
storage
256B (128 x 16) data flash memory
512 bytes (256 x 16) of SRAM for storage of temporary
variables
16-level stack memory for storage of program return
addresses and general-purpose use
The memory is arranged by default in a Harvard archi-
tecture, with separate address spaces for program and
data memory (see Figure 14). A special mode allows
data memory mapping into program space, permitting
code execution from data memory. Another mode allows
program memory mapping into data space, permitting
access to code constants as data memory.
The flash memory allows reprogramming the devices,
eliminating the expense of throwing away one-time pro-
grammable devices during development and field
upgrades (see Figure 15 for the flash memory sector
maps). Password protect flash memory with a 16-word
key to deny access to program memory by unautho-
rized individuals.
A pseudo-Von Neumann memory map places the utility
ROM, code, and data memory into a single contiguous
memory map. This is useful for applications that require
dynamic program modification or unique memory con-
figurations.
Stack Memory
A 16-bit-wide x 16 deep internal hardware stack pro-
vides storage for program return addresses and gener-
al-purpose use. The stack is used automatically by the
processor when the CALL, RET, and RETI instructions
are executed and interrupts serviced. The stack also
explicitly stores and retrieves data by using the PUSH,
POP, and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of the
stack (0Fh). The CALL, PUSH, and interrupt-vectoring
operations increment SP, then store a value at the location
pointed to by SP. The RET, RETI, POP, and POPI opera-
tions retrieve the value at SP and then decrement SP.
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