參數(shù)資料
型號(hào): MAXQ7666BATM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, QCC48
封裝: 7 X 7 MM, ROHS COMPLAINT, TQFN-48
文件頁(yè)數(shù): 17/49頁(yè)
文件大小: 2130K
代理商: MAXQ7666BATM+
MAXQ7666
16-Bit, RISC, Microcontroller-Based,
Smart Data-Acquisition System
24
_______________________________________________________________________________________
DGND
NOMINAL
DVDD (+3.3V)
BROWNOUT
RESET
+3.06V
+2.77V
INTERNAL RESET
BOR STATE
RESET OUTPUT
DVDD BROWNOUT
INTERRUPT
THRESHOLD RANGE
VDBI[1:0] = 01
+3.13V
+2.84V
BROWNOUT
RESET
TRIGGER
POINT
BROWNOUT
INTERRUPT
TRIGGER
POINT
BROWNOUT
INTERRUPT
DVLVL FLAG
(ASR[14])
POWER-UP*
DELAY
(8.6ms)
DVBI FLAG
(ASR[4])
FLAG ARBITRARILY
CLEARED BY
μC
*POWER-UP DELAY IS ONLY
PRESENT WHEN DVDD DROPS
BELOW ~1.2V
VDBE BIT SET BY
μC
DVDD BROWNOUT
RESET THRESHOLD
RANGE VDBR[1:0] = 01
Figure 5. DVDD Brownout Interrupt Detection
During power-up,
RESET is held low once DVDD rises
above +1.0V. All internal register bits are set to their
default, POR state after DVDD exceeds a threshold of
approximately +1.2V. DVDD brownout reset (BOR)
threshold defaults to the +2.70V to +2.99V range follow-
ing POR. Once DVDD rises above this DVDD brownout
threshold, the 7.6MHz RC oscillator starts driving the
power-up counter, and 8.6ms (typ) later,
RESET goes
high if nothing external holds it low. Ramp-up DVDD at a
rate of at least 35mV/ms between +2.7V and +3.0V to
ensure
RESET is held low before DVDD reaches a mini-
mum flash operating level of +3.0V. After DVDD reaches
a valid level and
RESET goes high, software execution
begins at the reset vector (8000h in the utility ROM).
Perform software clean-up when DVDD BOI is generat-
ed before DVDD BOR occurs. The amount of time
between BOI and BOR detection depends on the
brownout interrupt and reset threshold settings, the size
of the DVDD bypass capacitors, and the application-
dependent C power management and software
cleanup tasks. Use the internal +3.3V linear regulator
for additional software cleanup time by using the DVDDIO
brownout monitor as an early warning that the regula-
tor’s input voltage is falling.
RESET is pulled low when DVDD falls below the DVDD
BOR threshold set by the VDBR bits. Upon reset, the
C and peripheral activity stops and most registers are
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