參數(shù)資料
型號(hào): MAXQ7666BATM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, QCC48
封裝: 7 X 7 MM, ROHS COMPLAINT, TQFN-48
文件頁(yè)數(shù): 19/49頁(yè)
文件大小: 2130K
代理商: MAXQ7666BATM+
MAXQ7666
16-Bit, RISC, Microcontroller-Based,
Smart Data-Acquisition System
26
_______________________________________________________________________________________
As illustrated in Figure 7, the internal RC oscillator
(HFRCCLK) is the only clock source for the watchdog
timer (through a series of dividers). The divider output
is programmable and determines the timeout interval.
When enabled, the interrupt flag WDIF is set when a
timeout is reached. A system reset then occurs after a
time delay (based on the divider ratio).
The watchdog timer functions as the source of both the
watchdog interrupt and the watchdog reset. The interrupt
timeout has a default divide ratio of 212 of the HFRCCLK,
with the watchdog reset set to timeout 29 clock cycles
later. With the nominal RC oscillator value of 7.6MHz,
an interrupt timeout occurs every 539s, followed by a
watchdog reset 67.4s later. The watchdog timer resets
to the default divide ratio following any reset. Using the
WD0 and WD1 bits in the WDCN register, select other
divide ratios for longer watchdog interrupt periods. If
the WD[1:0] bits are changed before the watchdog
interrupt timeout occurs (i.e. before the watchdog reset
counter begins), the watchdog timer count is reset. All
watchdog timer reset timeouts follow the programmed
interrupt timeout 512 source clock cycles later. For
more information on the MAXQ7666 watchdog timer,
refer to the
MAXQ7665/MAXQ7666 User’s Guide.
Timer and PWM
The MAXQ7666 includes three 16-bit timers. Each timer
is a type 2 timer implemented in the MAXQ family (see
Figure 8). Two of the timers are accessible through I/Os
or software, and one is accessible only through soft-
ware. Type 2 timers are auto-reload 16-bit timers/coun-
ters offering the following functions:
8-bit/16-bit timer/counter
Up/down auto-reload
Counter function of external pulse
Capture
Compare
EDGE
DETECTION AND
GATING
TIMER EVENT
CCF[1:0]
G2EN
TR2
SS2
T2POL[0]
T2CL
T2MD
T2L COMPARE MATCH
T2H:T2L COMPARE MATCH OR
T2H COMPARE MATCH
T2L OVERFLOW
T2H:T2L OVERFLOW OR
T2H OVERFLOW
TR2L
T2CLK
T2L
T2RL
T2CH
T2H
T2RH
C/T2
Figure 8. Type 2 Timer Functional Diagram
EWDI
WD0
RWT
WD1
HFRCCLK
(7.6MHz)
INTERRUPT
WTRF
RESET
WDIF
TIMEOUT
TIME
212
DIV 212
DIV 23
215 218 221
EWT
RESET
Figure 7. Watchdog Functional Diagram
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