參數(shù)資料
型號(hào): MAX9796EBX+TG45
廠商: Maxim Integrated Products
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC AMP AUDIO 2.3W MONO D 36UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: DirectDrive®
類型: D 類
輸出類型: 1-通道(單聲道),帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 2.3W x 1 @ 4 歐姆
電源電壓: 2.7 V ~ 5.5 V
特點(diǎn): 消除爆音,差分輸入,I²C,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 36-UCSP
封裝/外殼: 36-WFBGA,CSBGA
包裝: 帶卷 (TR)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
______________________________________________________________________________________
19
I2C Interface
The MAX9796 features an I2C 2-wire serial interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate communication
between the MAX9796 and the master at clock rates up
to 400kHz. Figure 7 shows the 2-wire interface timing
diagram. The MAX9796 is a receive-only slave device
relying on the master to generate the SCL signal. The
master, typically a microcontroller, generates SCL and
initiates data transfer on the bus. The MAX9796 cannot
write to the SDA bus except to acknowledge the receipt
of data from the master. The MAX9796 does not
acknowledge a read command from the master.
A master device communicates to the MAX9796 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or REPEATED START (Sr) condition and a STOP (P) con-
dition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
The MAX9796 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9796 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9796 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure
8). A START condition from the master signals the
beginning of a transmission to the MAX9796. The mas-
ter terminates transmission and frees the bus by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tSU, STA
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 7. 2-Wire Serial-Interface Timing Diagram
SCL
SDA
SSr
P
Figure 8. START, STOP, and REPEATED START Conditions
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