參數(shù)資料
型號(hào): MAX9598CTL+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/36頁(yè)
文件大?。?/td> 0K
描述: IC SWITCH DUAL SCART 40TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
功能: 開(kāi)關(guān)
電路: 2 x SCART
導(dǎo)通狀態(tài)電阻: 7 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V,±11.4 V ~ 12.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(6x6)
包裝: 管件
Write Data Format
A write to the MAX9598 consists of transmitting a
START condition, the slave address with the R/W bit set
to 0, one data byte to configure the internal register
address pointer, 1 or more data bytes, and a STOP
condition. Figure 9 illustrates the proper frame format
for writing 1 byte of data to the MAX9598. Figure 10
illustrates the frame format for writing n bytes of data to
the MAX9598.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9598.
The MAX9598 acknowledges receipt of the address
byte during the master-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9598’s internal register address pointer.
The pointer tells the MAX9598 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9598 upon receipt of the address pointer data.
The third byte sent to the MAX9598 contains the data
that will be written to the chosen register. An acknowl-
edge pulse from the MAX9598 signals receipt of the
data byte. The address pointer autoincrements to the
next register address after each received data byte.
This autoincrement feature allows a master to write to
sequential register address locations within one contin-
uous frame. The master signals the end of transmission
by issuing a STOP condition.
Read Data Format
The master presets the address pointer by first sending
the MAX9598’s slave address with the R/W bit set to 0
followed by the register address after a START condition.
The MAX9598 acknowledges receipt of its slave address
and the register address by pulling SDA low during the
ninth SCL clock pulse. A REPEATED START condition is
then sent followed by the slave address with the R/W bit
set to 1. The MAX9598 transmits the contents of the
specified register. Transmitted data is valid on the rising
edge of the master-generated serial clock (SCL). The
address pointer autoincrements after each read data
byte. This autoincrement feature allows all registers to be
read sequentially within one continuous frame. A STOP
condition can be issued after any number of read data
bytes. If a STOP condition is issued followed by another
read operation, the first data byte to be read will be from
the register address location set by the previous transac-
tion and not 00h and subsequent reads will autoincre-
ment the address pointer until the next STOP condition.
Attempting to read from register addresses higher than
01h results in repeated reads from a dummy register
containing FFh data. The master acknowledges receipt
of each read byte during the acknowledge clock pulse.
The master must acknowledge all correctly received
bytes except the last byte. The final byte must be fol-
lowed by a not acknowledge from the master and then a
STOP condition. Figures 11 and 12 illustrate the frame
format for reading data from the MAX9598.
MAX9598
Low-Power Audio/Video Switch for
Dual SCART Connectors
______________________________________________________________________________________
19
A
0
SLAVE ADDRESS
REGISTER ADDRESS
DATA BYTE
ACKNOWLEDGE FROM MAX9598
R/W
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9598
B1
B0
B3
B2
B5
B4
B7
B6
S
A
P
Figure 9. Writing a Byte of Data to the MAX9598
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9598
B1 B0
B3 B2
B5 B4
B7 B6
A
0
ACKNOWLEDGE FROM MAX9598
R/W
S
A
1 BYTE
ACKNOWLEDGE FROM MAX9598
B1 B0
B3 B2
B5 B4
B7 B6
P
A
SLAVE ADDRESS
REGISTER ADDRESS
DATA BYTE 1
DATA BYTE n
Figure 10. Writing n Bytes of Data to the MAX9598
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