VIN1
參數(shù)資料
型號(hào)： MAX9526ATJ+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 38/38頁(yè)
文件大?。?/td> 0K
描述： IC VID DECODER NTSC/PAL 32-TQFN
其它有關(guān)文件： Automotive Product Guide
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： 視頻解碼器
應(yīng)用： 車載系統(tǒng)，播放器，電視
電壓 - 電源，模擬： 1.8V
電壓 - 電源，數(shù)字： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-TQFN-EP（5x6）
包裝： 帶卷 (TR)
Low-Power, High-Performance
NTSC/PAL Video Decoder
Pin Description
PIN
QSOP
TQFN-EP
NAME
FUNCTION
130
VIN1
Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1F
capacitor.
231
VREF
Video Reference Bypass. Bypass VREF to AGND with a 0.1F capacitor as close as
possible to the device.
332
VIN2
Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1F
capacitor.
4
1
AGND
Analog Ground
5
2
AVDD
Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a
0.1F capacitor.
6
3
XTAL2
External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2
when applying an external clock to XTAL/OSC.
7
4
XTAL/OSC
External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an
external clock source. Connect XTAL2 to the other terminal of the crystal oscillator.
8
5
I.C.
Internal connection. Connect to DGND.
9
6
DEVADR
I2C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3
available I2C slave addresses (see Table 5).
10, 22
7, 21
DVDD
Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a
0.1F capacitor in parallel with a 10F capacitor.
11, 23
8, 22
DGND
Digital Ground. Connect both DGND terminals together.
12
10
SDA
I2C-Compatible Serial-Data Input/Output. Connect a 10k
pullup resistor from SDA to
DVDDIO for full output swing.
13
11
SCL
I2C-Compatible Serial-Clock Input. Connect a 10k
pullup resistor from SCL to
DVDDIO for full output swing.
14
12
IRQ
Hardware Interrupt Open-Drain Output. If not masked, IRQ is pulled low when the bits
in the status register change state. Repeated faults have no effect on IRQ until IRQ is
cleared by reading the corresponding status register. Connect a 10k
pullup resistor
from IRQ to DVDDIO for full output swing.
15–20, 25–28
13–16, 18,
19, 24, 26,
27, 28
D0–D9
Digital Video Outputs Bit 0–Bit 9, 10-Bit Component Digital Video Outputs. The output
format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be
configured as horizontal and vertical sync outputs using the Clock and Output register
0x0D. D0 is LSB.
21
20
LLC
Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in
response to horizontal line rate of the incoming video. In async mode, the LLC clock is
synchronous to the crystal (see Table 1).
24
23
DVDDIO
Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to
DGND with a 0.1F capacitor.
—
9, 17, 25, 29
N.C.
No Connection. Not internally connected.
—
EP
Exposed Pad (TQFN Only). EP is internally connected to GND. Connect EP to GND.
MAX9526
Maxim Integrated
9
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