參數(shù)資料
型號(hào)： MAX9526ATJ+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 18/38頁(yè)
文件大小： 0K
描述： IC VID DECODER NTSC/PAL 32-TQFN
其它有關(guān)文件： Automotive Product Guide
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 視頻解碼器
應(yīng)用： 車(chē)載系統(tǒng)，播放器，電視
電壓 - 電源，模擬： 1.8V
電壓 - 電源，數(shù)字： 1.8V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-TQFN-EP（5x6）
包裝： 帶卷 (TR)
Low-Power, High-Performance
NTSC/PAL Video Decoder
Video Standard Select (STDSEL) Bit B7 (TYPE)
1 = NTSC J, PAL 60, NTSC 4.43.
0 = NTSC M (standard NTSC), PAL M, PAL B/G/H/I/D
(standard PAL), PAL Combination N (default).
Bit B6 (525 Line)
1 = 525 line video.
0 = 625 line video (or NTSC 4.43) (default).
Bit B6 sets the video line rate when AUTOD = 0. When
AUTOD = 1 (default), B6 is ignored.
Bit B5 (Unconventional Video)
1 = PAL Combination N, PAL M, NTSC 4.43, PAL 60.
0 = PAL B/G/H/I/D (standard PAL), NTSC M (standard
NSTC), or NTSC J (default).
The 3 bits in the STDSEL register can be used to pro-
gram the expected input video format. Bit B6 (525 vs.
625 line video) can be automatically set by using the
autodetect function (see AUTOD bit description, regis-
ter 0x04, B4).
B[7:5]
000:
PAL B/G/H/I/D (standard PAL)
001:
PAL Combination N
010:
NTSC M (standard NTSC)
011:
PAL M
100:
N/A
101:
NTSC 4.43
110:
NTSC J
111:
PAL60
Standard Autodetect (AUTOD)
1 = Automatically detects 525 vs. 625 line video
(default).
0 = Manually programs 525 vs. 625 line video.
Autodetect function can only be used to distinguish
between standard PAL and standard NTSC. The
autodetect function requires register 0x04, B7 = B5 = 0.
Low-Power Shutdown (SHDN)
1 = Low-power shutdown mode.
0 = Normal operation (default).
In shutdown, all logic outputs are low (unless pro-
grammed to high impedance using register 0x0D, B1).
I2C register contents are retained during shutdown.
System Reset (RESET)
1 = All registers and system state returned to power-on
default conditions.
0 = Normal operation (default).
Because all registers’ contents are set to power-on
default state, this bit clears itself after being written.
Sleep Mode (SLEEP)
1 = Low-power sleep mode.
0 = Normal operation (default).
In sleep mode, all logic outputs are low (unless pro-
grammed to high impedance using register 0x0D, B1).
I2C register contents are retained. Video activity detect
is still active. Activity status is available in register 0x00.
Soft Reset (RESET_S)
This bit resets everything on the device except the reg-
ister values. This bit is self-clearing.
1 = Soft reset.
0 = Normal operation (default).
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x04
STDSEL
AUTOD
SHDN
RESET
SLEEP
RESET_S
Standard Select, Shutdown, and Control Register
MAX9526
Maxim Integrated
25
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