1-to-8 I2C Bus Switches/Multiplexers with Bus Lock-Up De" />
參數(shù)資料
型號: MAX7358EUG+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/22頁
文件大?。?/td> 0K
描述: IC MULTIPLEXER 8X1 24TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 多路復(fù)用器
電路: 1 x 8:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
MAX7356/MAX7357/MAX7358
1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
______________________________________________________________________________________
17
2 seconds. The interrupt signal asserts again once a
new lock-up is detected. The interrupt signal does not
activate the reset function.
Serial Interface
Serial Addressing
The MAX7356/MAX7357/MAX7358 operate as a slave
that sends and receives data through an I2C interface.
The interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). The master initiates all
data transfers to and from the MAX7357 or MAX7358
and generates the SCL clock that synchronizes the
data transfer.
SDA operates as both an input and an open-drain out-
put. A pullup resistor (4.7k
, typ) is required on SDA.
SCL operates only as an input. A pullup resistor (4.7k
,
typ) is required on SCL if there are multiple masters on
the 2-wire interface, or if the master in a single-master
system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7356/MAX7357/
MAX7358’s 7-bit slave address plus R/
W bit, and then
optionally 1 or more data bytes, and finally a STOP con-
dition (Figure 10).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. The master signals the beginning of a trans-
mission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 11).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 12).
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient
uses to handshake receipt of each byte of data (Figure
13). Each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX7356/MAX7357/MAX7358, the
MAX7356/MAX7357/MAX7358 generate the acknowl-
START
0
A
0
1
0
1
0
S
0
L
1
W
ACKNOWLEDGE FROM
THE TROUBLED DEVICE
LOCK-UP
OCCURS
FIRST DATA BYTE
SECOND DATA BYTE
Figure 10. Bus Lock-Up During a 3-Byte Write Command
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 11. Start and Stop Conditions
SDA
SCL
DATA STABLE
DATA VALID
CHANGE OF
DATA ALLOWED
Figure 12. Bit Transfer
CLOCK PULSE FOR
ACKNOWLEDGMENT
NOT ACKNOWLEDGE
ACKNOWLEDGE
12
8
9
SDA
SCL
START
CONDITION
Figure 13. Acknowledge
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